ST62T65CM6 STMicroelectronics, ST62T65CM6 Datasheet - Page 58

IC MCU 8BIT OTP/EPROM 28 PSOIC

ST62T65CM6

Manufacturer Part Number
ST62T65CM6
Description
IC MCU 8BIT OTP/EPROM 28 PSOIC
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet

Specifications of ST62T65CM6

Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LED, LVD, POR, WDT
Number Of I /o
21
Program Memory Size
3.8KB (3.8K x 8)
Program Memory Type
OTP
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 13x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST6
No. Of I/o's
21
Eeprom Memory Size
128Byte
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST62T6x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2103-5
ST6255C ST6265C ST6265B
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
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a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whether the branch is a forward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to the address of the relative instruction to
obtain the address of the branch.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.

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