HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 238

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Interrupt Controller (INTC)
7.3.2
The ICR0 is a register that sets the input signal detection mode of the external interrupt input pin
NMI and indicates the input signal level to the NMI pin. This register is initialized to H'0000 or
H'8000 at power-on reset or manual reset, but is not initialized in standby mode.
Note: * When NMI input is high: 1; when NMI input is low: 0.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
0
1
Bit 8—NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt
request signal to the NMI is detected.
Bit 8: NMIE
0
1
Bits 14 to 9 and 7 to 0—Reserved: These bits are always read as 0. The write value should
always be 0.
Rev.6.00 Mar. 27, 2009 Page 180 of 1036
REJ09B0254-0600
Initial value:
Initial value:
Interrupt Control Register 0 (ICR0)
R/W:
R/W:
Bit:
Bit:
Description
NMI input level is low
NMI input level is high
Description
Interrupt request is detected on the falling edge of NMI input
Interrupt request is detected on rising edge of NMI input
NMIL
0/1*
15
—
R
R
7
0
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
11
—
—
R
R
0
3
0
10
—
—
R
R
0
2
0
—
—
R
R
0
9
0
1
(Initial value)
NMIE
R/W
—
R
8
0
0
0