HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 683

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit10—Receive Control Data Ready Enable (RCRDYE)
Bit10: RCRDYE
0
1
Bit 9—Receive FIFO Full Enable (RFFULE)
Bit 9: RFFULE
0
1
Bit 8—Receive Data Transfer Request Enable (RDREQE)
Bit 8: RDREQE
0
1
Bit 4—Frame Synchronization Error Enable (FSERRE)
Bit 4: FSERRE
0
1
Bit 3—Transmit FIFO Over Run Enable (TFOVRE)
Bit 3: TFOVRE
0
1
Bit 2—Transmit FIFO Under Run Enable (TFUDRE)
Bit 2: TFUDRE
0
1
Description
Disable interrupt of receive control data ready
Enable interrupt of receive control data ready (control interrupt)
Description
Disable interrupt of receive FIFO full
Enable interrupt of receive FIFO full (control interrupt)
Description
Disable interrupt of receive data transfer request
Enable interrupt of receive data transfer request (receive interrupt)
Description
Disable interrupt of frame synchronization error
Enable interrupt of frame synchronized error (error interrupt)
Description
Disable interrupt of transmit FIFO over run
Enable interrupt of transmit FIFO over run (error interrupt)
Description
Disable interrupt of transmit FIFO under run
Enable interrupt of transmit FIFO under run (error interrupt)
Rev.6.00 Mar. 27, 2009 Page 625 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)