HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 929

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

28.4.3
Scan mode is useful for monitoring analog inputs in a group of one or more channels including
channel 1. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software
or external trigger input, A/D conversion starts on the first channel in the group (AN2 when CH2
= 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first
channel ends, conversion of the second channel (AN3 or AN5) starts immediately. A/D
conversion is repeated continuously on the selected channels until the ADST bit is cleared to 0.
The conversion results are transferred for storage into the A/D data registers corresponding to the
channels.
When the mode or analog input channel must be changed during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the
necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel
in the group. The ADST bit can be set at the same time as the mode or channel selection is
changed.
Typical operations when three channels (AN4 to AN6) are selected in scan mode are described
next. Figure 28.5 shows a timing diagram for this example.
1. Scan mode is selected (MULTI = 1, SCN = 1), channel group 1 is selected (CH2 = 1), analog
2. When A/D conversion of the first channel (AN4) is completed, the result is transferred into
3. Conversion proceeds in the same way through the third channel (AN6).
4. When conversion of all the selected channels (AN4 to AN6) is completed, the ADF flag is set
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
input channels AN4 to AN6 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started
(ADST = 1).
ADDRA. Next, conversion of the second channel (AN5) starts automatically.
to 1 and conversion of the first channel (AN4) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN4).
Scan Mode (MULTI = 1, SCN = 1)
Rev.6.00 Mar. 27, 2009 Page 871 of 1036
Section 28 A/D Converter
REJ09B0254-0600