HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 445

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.2.4
Notes: 1. Only a write of 0 after a read of 1 is enabled for the TE bit.
The DMA channel control registers 0 to 3 (CHCR0 to CHCR3) are 32-bit read/write registers that
specify operation mode, transfer method, or others in each channel. Writing to bits 31 to 21 and 7
in this register is invalid, and these bits are always read as 0.
Bit 20 is only used in CHCR3. It is not used in CHCR0 to CHCR2. Consequently, writing to this
bit is invalid in CHCR0 to CHCR2, and this bit is always read as 0.
Bit 19 is only used in CHCR2. It is not used in CHCR0, CHCR1, and CHCR3. Consequently,
writing to this bit is invalid in CHCR0, CHCR1, and CHCR3, and this bit is always read as 0.
Bits 6 and 16 to 18 are only used in CHCR0 and CHCR1. They are not used in CHCR2 and
CHCR3. Consequently, writing to these bits is invalid in CHCR2 and CHCR3, and these bits are
always read as 0.
These registers are initialized to 0 after a power-on reset. The previous values are held in standby
mode.
Bits 31 to 21—Reserved: These bits are always read as 0 and should only be written with 0.
Initial value:
Initial value:
Initial value:
2. DI, RO, RL, AM, AL, and DS bits are not included in some channels.
DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
DM1
R/W
31
15
—
—
R
R
0
0
7
0
(R/W) *
DM0
R/W
DS
14
...
...
...
...
0
6
0
2
SM1
R/W
R/W
TM
21
13
—
R
0
0
5
0
Section 14 Direct Memory Access Controller (DMAC)
(R/W) *
SM0
R/W
R/W
TS1
20
12
DI
0
0
4
0
Rev.6.00 Mar. 27, 2009 Page 387 of 1036
2
(R/W) *
RS3
R/W
R/W
TS0
RO
19
11
0
0
3
0
2
(R/W) *
RS2
R/W
R/W
RL
18
10
IE
0
0
2
0
2
REJ09B0254-0600
(R/W) *
R/(W) *
RS1
R/W
AM
TE
17
0
9
0
1
0
2
1
(R/W) *
RS0
R/W
R/W
DE
AL
16
0
8
0
0
0
2