HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 680

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial IO (SIOF)
value of RFWM bit of SIMDR register. SIOF issues a receive interrupt if the interrupt issuing is
allowed for this bit.
Bit 8: RDREQ
0
1
Bit 4—Frame Synchronization Error (FSERR): Frame synchronization error shows that next
frame synchronize timing has come before data or control command are transferred. When frame
synchronization error has occurred , SIOF transmits or receives data to the slots that are enable to
transmit or receive data.
This bit becomes effective when 1 is written to TXE bit or RXE bit of SICTR register. This bit is
cleared when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing
is allowed to this bit.
Bit 4: FSERR
0
1
Bit 3—Transmit FIFO Over Run (TFOVR): Transmit FIFO overrun shows that data are written
to SITDR register when transmit FIFO is full. Written data is ignored when Transmit FIFO over
run happens.
This bit is effective when 1 is written to TXE bit of SICTR register. This bit is cleared when 1 is
written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this
bit.
Bit 3: TFOVR
0
1
Bit 2—Transmit FIFO Under Run (TFUDR):Transmit FIFO under run shows that the load by
data transfer from FIFO has occurred when transmit FIFO is empty.
SIOF repeats to send the data that was sent before when this under run has occurred.
Rev.6.00 Mar. 27, 2009 Page 622 of 1036
REJ09B0254-0600
Description
Effective data in receive FIFO does not exceed setting of RFWM bit of SIMDR
register
Effective data in receive FIFO exceeds setting of RFWM bit of SIMDR register
Description
Frame synchronization error does not occur
Frame synchronization error occurs
Description
Transmit FIFO over run does not occur
Transmit FIFO over run occurs
(Initial value)
(Initial value)
(Initial value)