HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 604

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Smart Card Interface
18.2
This section describes the registers added for the smart card interface and the bits whose functions
are changed.
18.2.1
The smart card mode register (SCSCMR) is an 8-bit read/write register that selects smart card
interface functions. SCSCMR bits 0, 2, and 3 are initialized to H’00 by a reset and in standby
mode.
Bits 7 to 4 and 1—Reserved: These bits are always read as 0. The write value should always be
0.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3: SDIR
0
1
Bit 2—Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the
data. This function is used in combination with bit 3 for transmitting and receiving with an inverse
convention card. SINV does not affect the logic level of the parity bit. See section 18.3.4, Register
Settings, for information on how parity is set.
Bit 2: SINV
0
1
Rev.6.00 Mar. 27, 2009 Page 546 of 1036
REJ09B0254-0600
Initial value:
Register Descriptions
Smart Card Mode Register (SCSCMR)
R/W:
Bit:
Description
Contents of SCTDR are transferred as LSB first, receive data is stored in
SCRDR as LSB first.
Contents of SCTDR are transferred as MSB first, receive data is stored in
SCRDR as MSB first.
Description
Contents of SCTDR are transferred unchanged, receive data is stored in SCRDR
unchanged.
Contents of SCTDR are inverted before transfer, receive data is inverted before
storage in SCRDR.
—
—
R
7
—
—
R
6
—
—
R
5
—
—
R
4
SDIR
R/W
3
0
SINV
R/W
2
0
—
—
R
1
(Initial value)
(Initial value)
SMIF
R/W
0
0