HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 832

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 LCD Controller
25.2.5
LDSARU sets the start address from which data is fetched by the LCDC for upper display of the
LCDC panel. When a DSTN panel is used, this register specifies the fetch start address for the
upper side of the panel.
Bits 31 to 26—Reserved
Bits 25 to 0—Start Address for Upper Display Data Fetch (SAU31 to SAU0): The start
address for data fetch of the display data must be set within the synchronous DRAM area of area
3.
Notes: 1. When using the hardware rotation function (ROT = 1), set the LDSARU value so that
Rev.6.00 Mar. 27, 2009 Page 774 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
2. When the hardware rotation function is used (ROT = 1), set the upper-left address of
LCDC Start Address Register for Upper Display Data Fetch (LDSARU)
SAU15 SAU14 SAU13 SAU12 SAU11 SAU10 SAU9
the upper-left address of the image is aligned with the 512-byte boundary.
the image which can be calculated from the display image size in this register. The
equation below shows how to calculate the LDSARU value when the image size is 240
×
from the memory size of the image to be displayed. Note that LDLAOR must be a
binary exponential at least as large as the horizontal width of the image. Calculate
backwards using the LDSARU value (LDSARU − 256 (LDLAOR value)
to ensure that the upper-left address of the image is aligned with the 512-byte
boundary.
LDSARU = (upper-left address of image) + 256 (LDLAOR value)
R/W
R/W
31
15
—
0
0
340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but
R/W
R/W
30
—
14
0
0
R/W
R/W
29
13
—
0
0
R/W
R/W
28
12
—
0
0
R/W
R/W
27
11
—
1
0
R/W
R/W
26
10
—
1
0
SAU25 SAU24 SAU23 SAU22 SAU21 SAU20 SAU19 SAU18 SAU17 SAU16
R/W
R/W
25
0
9
0
SAU8
R/W
R/W
24
0
8
0
SAU7
R/W
R/W
23
0
7
0
SAU6
R/W
R/W
22
0
6
0
SAU5
R/W
R/W
21
0
5
0
SAU4
R/W
R/W
20
0
4
0
SAU3
R/W
R/W
×
19
0
3
0
319 (line)
SAU2
R/W
R/W
18
0
2
0
×
(320 − 1))
SAU1
R/W
R/W
17
0
1
0
SAU0
R/W
R/W
16
0
0
0