HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 816

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 24 USB HOST Module
Data is filled from the lower bits of the memory in writing so that the data is read/written in bi-
direction consistently regardless of the endian type. That is, the data is always aligned with the
little endian specification.
24.3.2
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of USB
Host Controller must be aligned so that each Dword corresponds to the long-word boundary
(addresses 4n to 4n + 3) of the memory.
24.4
24.4.1
The transferred data is stored in shared system memory with CPU. The data alignment in system
memory are restricted depends on synchronous DRAM specification which is used as system
memory.
In above figure, transfer data 1 and 3 are able to be read or written by USB Host Controller. But
transfer data 2 are possibly unable to be read or written by USB Host controller. Any data which
have possibility to be accessed by USB Host Controller must be aligned in synchronous DRAM
not to cross row address alignment.
Rev.6.00 Mar. 27, 2009 Page 758 of 1036
REJ09B0254-0600
Storage Format of the Descriptor
Data Alignment Restriction of USB Host Controller
Restriction on the Line Boundary of the Synchronous DRAM
DRAM
Row address
Row address
Row address
n
n+1
n+2
Memory area
(2)
(3)
(1)