HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 553

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

17.2.7
Note: * The only value that can be written is a 0 to clear the flag.
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate SCI operating state.
The CPU can always read and write the SCSSR, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
The SCSSR is initialized to H'84 by a reset or in standby and module standby modes.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the SCTDR into the SCTSR and new serial transmit data can be written in the SCTDR.
Bit 7: TDRE
0
1
Initial value:
Serial Status Register (SCSSR)
R/W:
Bit:
Description
SCTDR contains valid transmit data
[Clear condition]
When software reads TDRE after it has been set to 1, then writes 0 in TDRE or
data is written in SCTDR.
SCTDR does not contain valid transmit data
[Setting conditions]
1. When the chip is reset or enters standby mode
2. When the TE bit in the serial control register (SCSCR) is cleared to 0
3. When SCTDR contents are loaded into SCTSR, so new data can be written
R/(W)*
in SCTDR.
TDRE
7
1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
Section 17 Serial Communication Interface (SCI)
R/(W)*
FER
4
0
Rev.6.00 Mar. 27, 2009 Page 495 of 1036
R/(W)*
PER
3
0
TEND
R
2
1
REJ09B0254-0600
MPB
R
1
0
(Initial value)
MPBT
R/W
0
0