HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 285

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.3.8
Break Condition Specified to a CPU Instruction Fetch Cycle
1. Register specifications
2. Register specifications
BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300400
Specified conditions: Channel A/channel B independent mode
•
•
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of adresses H'00008010 to H'00008016 are executed.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B sequence mode
•
•
Address:
Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not
No ASID check is included
Address:
Data:
Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not
No ASID check is included
Address:
Bus cycle: CPU/instruction fetch (before instruction execution)/read/word
Address:
Data:
Bus cycle: CPU/instruction fetch (before instruction execution)/read/word
Channel A
Channel B
Channel A
Channel B
Usage Examples
H'00000404, Address mask: H'00000000
included in the condition)
H'00008010, Address mask: H'00000006
H'00000000, Data mask: H'00000000
included in the condition)
H'00037226, Address mask: H'00000000, ASID = H'80
H'0003722E, Address mask: H'00000000, ASID = H'70
H'00000000, Data mask: H'00000000
Rev.6.00 Mar. 27, 2009 Page 227 of 1036
Section 8 User Break Controller
REJ09B0254-0600