UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 258

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
6.6.6 CPU clock status transition diagram
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Figure 6-17 and 6-18 shows the CPU clock status transition diagram of this product.
Note Standard and (A) grade products: 1.8 V,
Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
(A2) grade products: 2.7 V
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to
45
μ
s).
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0), 78K0/KB2)
(E)
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
oscillation/EXCLK
input
CPU: X1
HALT
Figure 6-17. CPU Clock Status Transition Diagram
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
(A)
(B)
with X1 oscillation or
Reset release
with internal high-
speed oscillation
CPU: Operating
(C)
CPU: Operating
Power ON
EXCLK input
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
(F)
(D)
(G)
CHAPTER 6 CLOCK GENERATOR
CPU: Internal high-
oscillation/EXCLK
CPU: Internal high-
speed oscillation
speed oscillation
input
CPU: X1
STOP
HALT
V
V
V
STOP
DD
DD
DD
< 1.59 V (TYP.)
1.59 V (TYP.)
1.8 V (MIN.)
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
Note
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