UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 87

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
2.2.10 P130 (port 13)
Note This is not mounted onto 38-pin and 44-pin products of the 78K0/KC2.
Remarks 1. When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before the
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
P130
P130 functions as an output-only port.
(b) EXLVI
(c) X1, X2
(d) EXCLK
(e) XT1, XT2
(f) EXCLKS
This is a potential input pin for external low-voltage detection.
These are the pins for connecting a resonator for main system clock.
This is an external clock input pin for main system clock.
These are the pins for connecting a resonator for subsystem clock.
This is an external clock input pin for subsystem clock.
Caution
Remark
2. √: Mounted, −: Not mounted
device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the figure
for Remark in 5.2.10 Port 13).
X1 and X2 of the product with an on-chip debug function (
used as on-chip debug mode setting pins (OCD0A and OCD0B) when the on-chip debug function is
used. For how to connect an on-chip debug emulator (QB-MINI2), see CHAPTER 28 ON-CHIP
DEBUG FUNCTION (
Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug function
(
memory programmer or an on-chip debug emulator.
μ
PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is connected to a flash
Flash memory programmer connection
On-chip debug
emulator connection
(when it is not used
as an on-chip debug
mode setting pin)
78K0/KB2
−
78K0/KC2
μ
√
PD78F05xxD and 78F05xxDA ONLY).
Note
During reset
During reset released
78K0/KD2
Connect to V
Input:
Output: Leave open.
whose flash
memory is
Products
less than
32 KB
Connect to V
resistor.
78K0/KE2
μ
P121/X1/OCD0A
PD78F05xxD and 78F05xxDA) can be
SS
√
via a resistor.
CHAPTER 2 PIN FUNCTIONS
memory is at
whose flash
Products
48 KB
least
DD
or V
SS
via a
78K0/KF2
87