UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 681

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
0000H and 0001H when the reset signal is generated.
voltage detection, and each item of hardware is set to the status shown in Tables 23-1 and 23-2. Each pin is high
impedance during reset signal generation or during the oscillation stabilization time just after a reset release, except for
P130, which is low-level output.
input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal high-
speed oscillation clock (see Figures 23-2 to 23-4) after reset processing. Reset by POC and LVI circuit power supply
detection is automatically released when V
internal high-speed oscillation clock (see CHAPTER 24
VOLTAGE DETECTOR) after reset processing.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The reset function is mounted onto all 78K0/Kx2 microcontroller products.
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address at
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
Cautions 1. For an external reset, input a low level for 10
Notes 1.
2.
2. During reset signal generation, the X1 clock, XT1 clock
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
The 78K0/KB2 is not provided with XT1 clock and external subsystem clock.
P130 pin is not mounted onto 38-pin and 44-pin products of the 78K0/KC2 and 78K0/KB2.
and internal low-speed oscillation clock stop oscillating. External main system clock input and
external subsystem clock
input. However, the port pins become high-impedance, except for P130
level output.
CHAPTER 23 RESET FUNCTION
DD
Note 1
≥ V
input become invalid.
POC
or V
DD
≥ V
POWER-ON-CLEAR CIRCUIT and CHAPTER 25
LVI
μ
s or more to the RESET pin.
after the reset, and program execution starts using the
Note 1
, internal high-speed oscillation clock,
CHAPTER 23 RESET FUNCTION
Note 2
, which is set to low-
LOW-
681