UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 944

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
This appendix lists cautions described in this document.
“Classification (hard/soft)” in table is as follows.
Hard:
Soft:
Pin function
Pin function
Memory
space
Function
Cautions for microcontroller internal/external hardware
Cautions for software such as register settings or programs
AV
AV
EV
REGC
ANI0/P20 to
ANIn/P2n
ANI0/P20 to
ANI7/P27
P31/INTP2/
OCD1A
P121/X1/OCD0A Process the P121/X1/OCD0A pin of the products mounted with the on-chip debug
REGC pin
IMS, IXS: Internal
memory size
switching register,
internal expansion
RAM size
switching register
Memory bank
SFR: Special
function register
SP: Stack pointer Since reset signal generation makes the SP contents undefined, be sure to initialize
SS
SS
DD
Details of
Function
, EV
SS
Make AV
Make AV
Make EV
Connect the REGC pin to V
ANI0/P20 to ANIn/P2n are set in the analog input mode after release of reset.
ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset.
In the product with an on-chip debug function (
sure to pull the P31/INTP2/OCD1A pin down before a reset, release to prevent
malfunction.
Process the P31/INTP2/OCD1A pin of the products mounted with the on-chip debug
function (
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.83).
function (
connected to a flash memory programmer or an on-chip debug emulator (see the
table on p.87).
Keep the wiring length as short as possible for the broken-line part in the above
figure.
Regardless of the internal memory capacity, the initial values of the internal memory
size switching register (IMS) and internal expansion RAM size switching register
(IXS) of all products in the 78K0/Kx2 microcontrollers are fixed (IMS = CFH, IXS =
0CH). Therefore, set the value corresponding to each product as indicated below.
To set the memory size, set IMS and then IXS. Set the memory size so that the
internal ROM and internal expansion RAM areas do not overlap.
Instructions cannot be fetched between different memory banks.
Branch and access cannot be directly executed between different memory banks.
Execute branch or access between different memory banks via the common area.
Allocate interrupt servicing in the common area.
An instruction that extends from 7FFFH to 8000H can only be executed in memory
bank 0.
Do not access addresses to which SFRs are not assigned.
the SP before using the stack.
APPENDIX D LIST OF CAUTIONS
SS
SS
DD
μ
μ
PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is
PD78F05xxD and 78F05xxDA) as follows, when it is not used when it is
the same potential as V
and EV
the same potential as V
SS
the same potential as V
SS
via a capacitor (0.47 to 1
SS
DD
.
.
Cautions
SS
μ
.
PD78F05xxD and 78F05xxDA), be
APPENDIX D LIST OF CAUTIONS
μ
F).
pp. 42,
44 to 47
pp. 43,
48 to 50
pp. 43,
48 to 50
pp. 42 to
50
pp. 42 to
50
p. 81
p. 82
p. 83
p. 87
p. 90
p. 96
p. 96
p. 113
p. 113
p. 113
p. 113
p. 116
p. 126
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