UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 951

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
16-bit
timer/event
counters 00,
01
Function
PRM0n: Prescaler
mode register 0n
Clear & start
mode entered by
TI00n pin valid
edge input
PPG output
One-shot pulse
output
LVS0n, LVRn0
Timer start errors An error of up to one clock may occur in the time required for a match signal to be
CR00n, CR01n:
16-bit timer
capture/compare
registers 00n, 01n
Details of
Function
−
• Clear & start mode entered by the TI00n pin valid edge
• Setting the TI00n pin as a capture trigger
Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to 11
(to specify the valid edge of the TI00n pin as a count clock).
If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or
TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is
specified to be the rising edge or both edges, the high level of the TI00n or TI01n
pin is detected as a rising edge. Note this when the TI00n or TI01n pin is pulled up.
However, the rising edge is not detected when the timer operation has been once
stopped and then is enabled again.
The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at
the same time, and the valid edge of TI011 and timer output (TO01) cannot be used
for the P06 pin at the same time. Select either of the functions.
Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and
PRM0n0 = 11). When PRM0n1 and PRM0n0 = 11, TM0n may be cleared.
To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting
CR01n during TM0n operation.
Set values to CR00n and CR01n such that the condition 0000H ≤ CR01n < CR00n
≤ FFFFH is satisfied.
Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of
the TI00n pin) while the one-shot pulse is output. To output the one-shot pulse
again, generate the trigger after the current one-shot pulse output has completed.
To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do
not change the level of the TI00n pin or its alternate function port pin. Otherwise,
the pulse will be unexpectedly output.
Do not set the same value to CR00n and CR01n.
Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above.
Step <2> can be performed after <1> and before <3>.
Table 7-3 shows the restrictions for each channel.
generated after timer start. This is because counting TM0n is started
asynchronously to the count pulse.
Set a value other than 0000H to CR00n and CR01n in clear & start mode entered
upon a match between TM0n and CR00n (TM0n cannot count one pulse when it is
used as an external event counter).
When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the
TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture
operation but the read value of CR00n/CR01n is not guaranteed. At this time, an
interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the
TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-
phase edge of the TI00n pin is detected).
When the count value is captured because the valid edge of the TI00n/TI01n pin
was detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is
generated.
The values of CR00n and CR01n are not guaranteed after 16-bit timer/event
counter 0n stops.
Cautions
APPENDIX D LIST OF CAUTIONS
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