UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 498

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(3) Port mode registers 0 and 1 (PM0, PM1)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 2.
Cautions 1. Do not write to CSIC11 while CSIE11 = 1 (operation enabled).
Remark f
These registers set port 0 and 1 input/output in 1-bit units.
When using P10/SCK10 and P04/SCK11 as the clock output pins of the serial interface, clear PM10 and PM04 to 0,
and set the output latches of P10 and P04 to 1.
When using P12/SO10 and P02/SO11 as the data output pins of the serial interface, clear PM12, PM02, and the
output latches of P12 and P02 to 0.
When using P10/SCK10 and P04/SCK11 as the clock input pins of the serial interface, P11/SI10/R
as the data input pins, and P05/SSI11/TI001 as the chip select input pin, set PM10, PM04, PM11, PM03, and PM05
to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1.
PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
3.
2. To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the default status
3. The phase type of the data clock is type 1 after reset.
PRS
Set the serial clock to satisfy the following conditions.
Do not start communication with the external clock from the SCK11 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
: Peripheral hardware clock frequency
(00H).
Supply Voltage
Remark The figure shown above presents the format of port mode register 0 of 78K0/KF2
DD
DD
DD
≤ 5.5 V
< 4.0 V
< 2.7 V
Address: FF20H
Symbol
Figure 16-7. Format of Port Mode Register 0 (PM0)
PM0
products. For the format of port mode register 0 of other products, see (1) Port mode
registers (PMxx) in 5.3 Registers Controlling Port Function.
Serial clock ≤ 6.25 MHz
Serial clock ≤ 4 MHz
Serial clock ≤ 2 MHz
PM0n
Standard Products
7
1
0
1
Conventional-specification Products (
PM06
Expanded-specification Products (
Output mode (output buffer on)
Input mode (output buffer off)
6
After reset: FFH
P0n pin I/O mode selection (n = 0 to 6)
PM05
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
5
PM04
4
Serial clock ≤ 5 MHz
Serial clock ≤ 2.5 MHz
Serial clock ≤ 1.66 MHz
PM03
R/W
3
(A) Grade Products
PM02
2
μ
μ
PM01
PD78F05xxA and 78F05xxDA)
PD78F05xx and 78F05xxD) and
1
PM00
0
Serial clock ≤ 5 MHz
Serial clock ≤ 2.5 MHz
(A2) Grade Products
−
X
D0 and P03/SI11
498