UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 289

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
7.4 Operation of 16-Bit Timer/Event Counters 00 and 01
7.4.1 Interval timer operation
mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the count
clock.
(INTTM00n) is generated. This INTTM00n signal enables TM0n to operate as an interval timer.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start
When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H and a match interrupt signal
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
Remark n = 0:
Compare match interrupt
2. For how to enable the INTTM00n interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
n = 0, 1: 78K0/KE2 products whose flash memory is at least 48 KB, and 78K0/KF2 products
(TMC0n3, TMC0n2)
Compare register
Count clock
TM0n register
Operable bits
(INTTM00n)
78K0/KD2 products
78K0/KE2 products whose flash memory is less than 32 KB, and 78K0/KB2, 78K0/KC2,
(CR00n)
TMC0n3, TMC0n2
0000H
Operable bits
Figure 7-17. Basic Timing Example of Interval Timer Operation
Figure 7-16. Block Diagram of Interval Timer Operation
00
Interval
(N + 1)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
N
16-bit counter (TM0n)
CR00n register
Clear
Interval
(N + 1)
N
Match signal
11
N
Interval
(N + 1)
N
INTTM00n signal
Interval
(N + 1)
N
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