UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 955

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Watchdog
timer
Clock output/
buzzer output
controller
A/D converter
Function
Operation control
Setting overflow
time of watchdog
timer, Setting
window open
period of
watchdog time
Setting window
open period of
watchdog timer
CKS: clock
output select
register
ADCR: 10-bit
A/D conversion
register, ADCRH:
8-bit A/D
conversion
register
ADM: A/D
converter mode
register
A/D conversion
timer selection
ADCR: 10-bit
A/D conversion
register
Details of
Function
The watchdog timer can be cleared immediately before the count value overflows
(FFFFH).
The operation of the watchdog timer in the HALT and STOP modes differs as
follows depending on the set value of bit 0 (LSROSC) of the option byte (see Table
on p. 402).
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP
mode is released. At this time, the counter is not cleared to 0 but starts counting
from the value at which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit
1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0, the
watchdog timer stops operating. At this time, the counter is not cleared to 0.
The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 =
WINDOW0 = 0 is prohibited.
The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer
at 1.8 V ≤ V
The first writing to WDTE after a reset release clears the watchdog timer, if it is
made before the overflow time regardless of the timing of the writing, and the
watchdog timer starts counting again.
Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0).
When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read
data from ADCR and ADCRH when the peripheral hardware clock (f
For details, see CHAPTER 36 CAUTIONS FOR WAIT.
A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to
values other than the identical data.
If data is written to ADM, a wait cycle is generated. Do not write data to ADM when
the peripheral hardware clock (f
CAUTIONS FOR WAIT.
Set the conversion times with the following conditions.
(see pp.414, 415)
When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D
conversion once (ADCS = 0) beforehand.
Change LV0 from the default value, when 2.3 V ≤ AV
The above conversion time does not include clock frequency errors. Select
conversion time, taking clock frequency errors into consideration.
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the
contents of ADCR may become undefined. Read the conversion result following
conversion completion before writing to ADM, ADS, and ADPC. Using timing other
than the above may cause an incorrect conversion result to be read.
If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR
when the peripheral hardware clock (f
36 CAUTIONS FOR WAIT.
DD
< 2.7 V.
PRS
) is stopped. For details, see CHAPTER 36
Cautions
PRS
) is stopped. For details, see CHAPTER
APPENDIX D LIST OF CAUTIONS
REF
< 2.7 V.
PRS
) is stopped.
p. 399
p. 400
pp. 400,
401
pp. 400,
401
p. 401
p. 401
pp. 405,
407
p. 407
p. 411
p. 413
p. 413
pp. 414,
415
pp. 414,
415
pp. 414,
415
pp. 414,
415
p. 416
p. 416
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