UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 438

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(2) Asynchronous serial interface reception error status register 0 (ASIS0)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FF73H After reset: 00H R
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
Symbol
ASIS0
This register indicates an error status on completion of reception by serial interface UART0. It includes three error
flag bits (PE0, FE0, OVE0).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation, or clearing bit 7 (POWER0) or bit 5 (RXE0) of ASIM0 to 0 clears this register to 00H. 00H is
read when this register is read. If a reception error occurs, read ASIS0 and then read receive buffer register 0 (RXB0)
to clear the error flag.
Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of stop
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0 (RXB0)
4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the
OVE0
asynchronous serial interface operation mode register 0 (ASIM0).
bits.
but discarded.
peripheral hardware clock (f
PE0
FE0
7
0
1
0
1
0
1
0
If POWER0 = 0 or RXE0 = 0, or if ASIS0 register is read.
If the parity of transmit data does not match the parity bit on completion of reception.
If POWER0 = 0 or RXE0 = 0, or if ASIS0 register is read.
If the stop bit is not detected on completion of reception.
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If receive data is set to the RXB0 register and the next reception operation is completed before the
data is read.
6
0
5
0
PRS
) is stopped. For details, see CHAPTER 36 CAUTIONS FOR WAIT.
Status flag indicating framing error
Status flag indicating overrun error
Status flag indicating parity error
4
0
CHAPTER 14 SERIAL INTERFACE UART0
3
0
PE0
2
FE0
1
OVE0
0
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