UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 578

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.11 Extension code
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC0)
(2) If “11110××0” is set to SVA0 register by a 10-bit address transfer and “11110××0” is transferred from the master
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth
clock. The local address stored in slave address register 0 (SVA0) is not affected.
device, the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match:
Remark
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next communication
operation.
Remark
Slave Address
EXC0: Bit 5 of IIC status register 0 (IICS0)
COI0: Bit 4 of IIC status register 0 (IICS0)
For extension codes other than the above, refer to THE I
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
Table 18-4. Bit Definitions of Main Extension Code
R/W Bit
COI0 = 1
0
0
1
General call address
10-bit slave address specification (for address authentication)
after address match)
10-bit slave address specification (for read command issuance
2
CHAPTER 18 SERIAL INTERFACE IIC0
Description
C-BUS SPECIFICATION published by NXP.
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