HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 214

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
4.4
4.4.1
The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of
256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The
SH7750R's instruction cache is 2-way set associative. Each way consists of 256 cache lines.
Figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750S.
Figure 4.7 shows the configuration of the instruction cache for the SH7750R.
Rev.7.00 Oct. 10, 2008 Page 128 of 1074
REJ09B0366-0700
Effective address
22
19
31
MMU
Instruction Cache (IC)
Configuration
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S)
IIX
26 25
8
255
[12]
0
Compare
Hit signal
Address array
19 bits
Tag
1 bit
V
3
13 12 11 10 9
Longword (LW) selection
32 bits
LW0
32 bits
LW1
32 bits
LW2
[11:5]
32 bits
LW3
Data array
Read data
5 4 3 2 1
32 bits
LW4
32 bits
LW5
0
32 bits
LW6
32 bits
LW7