HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 931

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.4.2
When handling multiple interrupts, interrupt handling should include the following procedures:
1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The
2. Clear the interrupt source in the corresponding interrupt handler.
3. Save SPC and SSR to the stack.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Set the BL bit in SR to 1.
7. Restore SSR and SPC from memory.
8. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4. This enables the interrupt response time to be
shortened for urgent processing.
19.4.3
By setting the MAI bit to 1 in the ICR register, it is possible to mask interrupts while the NMI pin
is low, irrespective of the BL and IMASK bits in the SR register.
• In normal operation and sleep mode
• In standby mode
code in INTEVT can be used as a branch-offset for branching to the specific handler.
All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is
generated by a transition at the NMI pin.
All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a
transition at the NMI pin. Therefore, standby cannot be cleared by an NMI interrupt while the
MAI bit is set to 1.
Multiple Interrupts
Interrupt Masking with MAI Bit
Rev.7.00 Oct. 10, 2008 Page 845 of 1074
Section 19 Interrupt Controller (INTC)
REJ09B0366-0700