HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 748

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting,
Bit 6: CHR
0
1
Note:
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit
addition and checking is not performed, regardless of the PE bit setting.
Bit 5: PE
0
1
Note:
Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and
checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition
and checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, and
when parity addition and checking is disabled in asynchronous mode.
Bit 4: O/E
0
1
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
Rev.7.00 Oct. 10, 2008 Page 662 of 1074
REJ09B0366-0700
*
*
2. When odd parity is set, parity bit addition is performed in transmission so that the total
When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted.
When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Description
8-bit data
7-bit data*
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
Description
Even parity *
Odd parity *
2
1
(Initial value)
(Initial value)
(Initial value)