HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 626

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
If a refresh request is generated when BACK has been asserted and the bus has been released, the
BACK signal is negated even while the BREQ signal is asserted to request the slave to relinquish
the bus. When this LSI is used in master mode, consecutive bus accesses may be attempted to
reduce the overhead due to arbitration in the case of a slave designed independently by the user.
When connecting a slave for which the total duration of consecutive accesses exceeds the refresh
cycle, the design should provide for the bus to be released as soon as possible after negation of the
BACK signal is detected.
13.3.13 Slave Mode
In slave mode, the bus is normally in the released state, and an external device cannot be accessed
unless the bus is acquired through execution of the bus arbitration sequence. In a reset, also, the
bus-released state is established and the bus arbitration sequence is started from the reset vector
fetch.
To acquire the bus, the slave device asserts (drives low) the BSREQ signal in synchronization
with the rising edge of the clock. The bus use permission BSACK signal is sampled for assertion
(low level) in synchronization with the rising edge of the clock. When BSACK assertion is
detected, the bus control signals and address bus are immediately driven at the negated level. The
bus cycle is started at the next rising edge of the clock. The last signal negated at the end of the
access cycle is synchronized with the rising edge of the clock. When the bus cycle ends, the
BSREQ signal is negated and the release of the bus is reported to the master. On the next rising
edge of the clock, the control signals are set to high-impedance.
In order for the slave mode processor to begin access, the BSACK signal must be asserted for at
least two cycles.
For a slave access cycle in DRAM or synchronous DRAM, the bus is released on completion of
precharging, as in the case of the master.
Refresh control is left to the master mode device, and any refresh control settings made in slave
mode are ignored.
Do not use DRAM/synchronous DRAM RAS down mode in slave mode.
Synchronous DRAM mode register settings should be made by the master mode device. Do not
use the DMAC's DDT mode in slave mode.
Rev.7.00 Oct. 10, 2008 Page 540 of 1074
REJ09B0366-0700