HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 689

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.5
14.5.1
Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT
mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via
the data bus and DDT module, and simultaneously issue a transfer request, using the DBREQ,
BAVL, TR, TDACK, and ID [1:0] signals between an external device and the DMAC. Figure
14.23 shows a block diagram of the DMAC, DDT, BSC, and an external device (with DBREQ,
BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR pins).
For channels 0 to 3, after making the settings for normal DMA transfer using the CPU, a transfer
request can be issued from an external device using the DBREQ, BAVL, TR, TDACK, ID [1:0],
and D [63:0] = DTR signals (handshake protocol using the data bus). A transfer request can also
be issued simply by asserting TR, without using the external bus (handshake protocol without use
of the data bus). For channel 2, after making the DMA transfer settings in the normal way, a
transfer request can be issued directly from an external device (with DBREQ, BAVL, TR,
TDACK, ID [1:0], and D [63:0] = DTR pins) by asserting DBREQ and TR simultaneously.
Note: DTR format = Data transfer request format
In DDT mode, there is a choice of five modes for performing DMA transfer.
ddtmode tdack id[1:0]
DMAC
BSC
On-Demand Data Transfer Mode (DDT Mode)
Operation
DMATCR0
DREQ0–3
CHCR0
SAR0
DAR0
Data buffer
Figure 14.23 On-Demand Transfer Mode Block Diagram
ddtmode
bavl
BAVL
DBREQ
TDACK
ID[1:0]
DDT
controller
Request
buffer
Data
Section 14 Direct Memory Access Controller (DMAC)
TR
Rev.7.00 Oct. 10, 2008 Page 603 of 1074
DTR
REJ09B0366-0700
DBREQ, BAVL,
TR, TDACK,
device (with
and ID [1:0])
memory
FIFO or
External
Memory