HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 752

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
0
1
Note:
Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data
transmission.
Bit 2: TEIE
0
1
Note:
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial
clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of
external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining
the SCI's operating mode with SCSMR1.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Rev.7.00 Oct. 10, 2008 Page 666 of 1074
REJ09B0366-0700
*
*
When receive data including MPB = 1 is received, the MPIE bit is cleared to 0
automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in
SCSCR1 are set to 1) and FER and ORER flag setting is enabled.
TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1,
then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0.
Description
Multiprocessor interrupts disabled (normal reception performed) (Initial value)
[Clearing conditions]
•
•
Multiprocessor interrupts enabled*
Description
Transmit-end interrupt (TEI) request disabled*
Transmit-end interrupt (TEI) request enabled*
When the MPIE bit is cleared to 0
When data with MPB = 1 is received
(Initial value)