HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 917

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 19.4 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1)
IRL3
1/0
1/0
1/0
0
19.2.3
On-chip peripheral module interrupts are generated by the following nine modules:
• High-performance user debug interface (H-UDI)
• Direct memory access controller (DMAC)
• Timer unit (TMU)
• Realtime clock (RTC)
• Serial communication interface (SCI)
• Serial communication interface with FIFO (SCIF)
• Bus state controller (BSC)
• Watchdog timer (WDT)
• I/O port (GPIO)
Not every interrupt source is assigned a different interrupt vector, bus sources are reflected in the
interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT register
value as a branch offset in the exception handling routine.
A priority level from 15 to 0 can be set for each module by means of interrupt priority registers A
to D (IPRA–IPRD), 00 (INTPRI00).
The interrupt mask bits (IMASK) in the status register (SR) are not affected by on-chip peripheral
module interrupt handling.
On-chip peripheral module interrupt source flag and interrupt enable flag updating should only be
carried out when the BL bit in the status register (SR) is set to 1. To prevent acceptance of an
erroneous interrupt from an interrupt source that should have been updated, first read the on-chip
peripheral register containing the relevant flag, then clear the BL bit to 0. In the case of interrupts
on channel 3 or 4 of the TMU, also read from the interrupt source register 00 (INTREQ00). This
On-Chip Peripheral Module Interrupts
IRL2
1/0
1/0
0
1
IRL1
1/0
0
1
1
IRL0
0
1
1
1
Interrupt Priority Level
13
10
7
4
Rev.7.00 Oct. 10, 2008 Page 831 of 1074
Section 19 Interrupt Controller (INTC)
Interrupt Request
IRL0
IRL1
IRL2
IRL3
REJ09B0366-0700