HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 253

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(4) Data TLB Protection Violation Exception
• Source: The access does not accord with the UTLB protection information (PR bits) shown
• Transition address: VBR + H'0000 0100
• Transition operations:
Data_TLB_protection_violation_exception()
{
}
below.
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR, and the contents of R15 are saved in SGR.
Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
PR
00
01
10
11
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = read_access ? H'000000A0 : H'000000C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
Privileged Mode
Only read access possible
Read/write access possible
Only read access possible
Read/write access possible
User Mode
Access not possible
Access not possible
Only read access possible
Read/write access possible
Rev.7.00 Oct. 10, 2008 Page 167 of 1074
Section 5 Exceptions
REJ09B0366-0700