HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 827

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected.
Bit 4: BRK
0
1
Note:
Bit 3—Framing Error (FER): Indicates whether or not a framing error has been found in the
data that is to be read next from SCFRDR2.
Bit 3: FER
0
1
*
When a break is detected, the receive data (H'00) following detection is not transferred
to SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive
data transfer is resumed.
Description
A break signal has not been received
[Clearing conditions]
•
•
A break signal has been received*
[Setting condition]
When data with a framing error is received, followed by the space “0” level
(low level ) for at least one frame length
Description
There is no framing error that is to be read from SCFRDR2
[Clearing conditions]
•
•
There is a framing error that is to be read from SCFRDR2
[Setting condition]
When there is a framing error in the data that is to be read next from
SCFRDR2
Power-on reset or manual reset
When 0 is written to BRK after reading BRK = 1
Power-on reset or manual reset
When there is no framing error in the data that is to be read next from
SCFRDR2
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev.7.00 Oct. 10, 2008 Page 741 of 1074
REJ09B0366-0700
(Initial value)
(Initial value)