HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 23

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
13.3.5 Synchronous
DRAM Interface
Figure 13.42 (2)
Synchronous DRAM
Mode Write Timing
(Mode Register Set)
Connecting a 128-
Mbit/256-Mbit
Synchronous DRAM
with 64-bit Bus Width
(SH7750R Only):
Figure 13.46
Synchronous DRAM
Auto-Refresh Timing
with 64-Bit Bus Width
(TRAS [2:0] = 001, TRC
[2:0] = 001))
13.3.7 PCMCIA
Interface
Figure 13.51 Basic
Timing for PCMCIA
Memory Card Interface
Figure 13.52 Wait
Timing for PCMCIA
Memory Card Interface
Page
491
494, 495 Description amended
496
505
506
Revision (See Manual for Details)
Figure amended
• In the auto-refresh operation, the REF command is issued
Figure newly added
Figure amended
Figure amended
CASS
D63–D0
CKE
WE1
(write)
D15–D0
(write)
twice continuously in response to a single refresh request.
The interval cycle number between the first and second REF
commands issuance is specified by the setting of the
TRAS2−TRAS0 bits in MCR, which is 4 to 11 CKIO cycles.
The interval cycle number between the second REF
command and the next ACTV command issuance is specified
by the settings of both the TRAS2−TRAS0 bits and the
TRC2−TRC0 bits in MCR in the sum total, which is 4 to 32
CKIO cycles. Set RTCOR and bits CKS2−CKS0, and MCR so
as to satisfy the refresh-interval rating of the synchronous
DRAM which you are using. The synchronous DRAM auto-
refresh timing with 64-bit bus width is shown below figure.
WE1
(write)
D15–D0
(write)
(High)
Rev.7.00 Oct. 10, 2008 Page xxi of lxxxiv
REJ09B0366-0700