HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 631

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.1
The SH7750 and SH7750S include an on-chip four-channel direct memory access controller
(DMAC). The SH7750R includes an on-chip eight-channel DMAC. The DMAC can be used in
place of the CPU to perform high-speed data transfers among external devices equipped with
DACK (TMU, SCI, SCIF), external memories, memory-mapped external devices, and on-chip
peripheral modules (except the DMAC, BSC, and UBC). Using the DMAC reduces the burden on
the CPU and increases the operating efficiency of the chip. When using the SH7750R, see the
following sections:
Section 14.6, Configuration of DMAC (SH7750R);
Section 14.7, Register Descriptions (SH7750R);
Section 14.8, Operation (SH7750R).
14.1.1
The DMAC has the following features.
• Four channels (SH7750/SH7750S), eight channels (SH7750R)
• Physical address space
• Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
• Maximum of 16 M (16,777,216) transfers
• Choice of single or dual address mode
• Choice of bus mode: Cycle steal mode or burst mode
• Two types of DMAC channel priority ranking:
⎯ Single address mode: Either the transfer source or the transfer destination (external device)
⎯ Dual address mode: Both the transfer source and transfer destination are accessed by
⎯ Fixed priority mode: Channel priorities are permanently fixed.
⎯ Round robin mode: Sets the lowest priority for the channel for which an execution request
Section 14 Direct Memory Access Controller (DMAC)
is accessed by a DACK signal while the other is accessed by address. One data transfer is
completed in one bus cycle.
address. Values set in DMAC internal registers indicate the accessed address for both the
transfer source and the transfer destination. Two bus cycles are required for one data
transfer.
was last accepted.
Overview
Features
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 545 of 1074
REJ09B0366-0700