HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 586

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
13.3.7
In this LSI, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory
space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA
specification version 4.2 (PCMCIA2.1).
Figure 13.50 shows an example of PCMCIA card connection to this LSI. To enable active
insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a
3-state buffer must be connected between this LSI's bus interface and the PCMCIA cards.
As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications,
this LSI supports only a little-endian mode PCMCIA interface.
In the SH7750, the PCMCIA interface area can only be accessed when the MMU is used. The
PCMCIA interface memory space can be set in page units and there is a choice of 8-bit common
memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O
space, 16-bit I/O space, or dynamic bus sizing, according to the accessed SA2 to SA0 bits.
Rev.7.00 Oct. 10, 2008 Page 500 of 1074
REJ09B0366-0700
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
CKIO
A25–A5
A4–A0
CSn
RD/WR
RD
D63–D0
(read)
BS
RDY
DACKn
(SA: IO ← memory)
PCMCIA Interface
TS1
T1
Figure 13.49 Burst ROM Wait Access Timing
TB2
TH1
TS1
TB1
TB2
TH1
TS1
TB1
TB2
TH1
TS1
TB1
T2
TH1