MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 217

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.3
Each chip select has a dedicated set of registers for configuration and control.
CS0 is a global chip select after reset and provides relocatable boot ROM capability.
12.3.1
When a bus cycle is initiated, the device first compares its address with the base address and mask
configurations programmed for chip selects 0–6 (configured in CSCR0–CSCR6) and DRAM blocks 0 and
1 (configured in DACR0 and DACR1). If the driven address matches a programmed chip select or DRAM
block, the appropriate chip select is asserted or the DRAM block is selected using the specifications
programmed in the respective configuration register. Otherwise, the following occurs:
Table 12-3
12.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See
Control Registers
Freescale Semiconductor
•
•
•
•
•
•
Chip select address registers (CSARn) control the base address of the chip select. See
Section 12.4.1.1, “Chip Select Address Registers
Chip select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 12.4.1.2, “Chip Select Mask Registers
Chip select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, and automatic acknowledge generation features. See
Control Registers
If the address and attributes do not match in CSAR or DACR, the device runs an external
burst-inhibited bus cycle with a default of external termination on a 32-bit port.
Should an address and attribute match in multiple CSCRs, the matching chip select signals are
driven; however, the chip select signals are driven during an external burst-inhibited bus cycle with
external termination on a 32-bit port.
If the address and attribute match both DACRs or a DACR and a CSAR, the operation is undefined.
Chip Select Operation
General Chip Select Operation
shows the type of access as a function of match in the CSARs and DACRs.
Number of CSCR Matches
(CSCR0–CSCR6)” for more information.
Multiple
Multiple
Multiple
0
1
0
1
0
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 12-3. Accesses by Matches in CSARs and DACRs
(CSCR0–CSCR6)”.
Number of DACR Matches
Multiple
Multiple
Multiple
0
0
0
1
1
1
(CSMR0–CSMR6)”.
(CSAR0–CSAR6)”.
Figure 12-1
External, burst-inhibited, 32-bit
Defined by DACRs
Defined by CSAR
Section 12.4.1.3, “Chip Select
Type of Access
Undefined
Undefined
Undefined
Undefined
Undefined
Section 12.4.1.3, “Chip Select
External
shows the correspondence
Chip Select Module
12-3