MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 400

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DMA Timers (DTIM0–DTIM3)
21.2.6
The current value of the 32-bit timer counter can be read at anytime without affecting counting. Writes to
DTCNn clear the timer counter. The timer counter increments on the clock source rising edge (internal bus
clock divided by 1, internal bus clock divided by 16, or DTINn).
21.3
21.3.1
The prescaler clock input is selected from the internal bus clock (f
corresponding timer input, DTINn. DTINn is synchronized to the internal bus clock, and the
synchronization delay is between two and three internal bus clocks. The corresponding DTMRn[CLK]
selects the clock input source. A programmable prescaler divides the clock input by values from 1 to 256.
The prescaler output is an input to the 32-bit counter, DTCNn.
21.3.2
Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when the
corresponding input capture edge detector senses a defined DTINn transition. The capture edge bits
(DTMRn[CE]) select the type of transition that triggers the capture and sets the timer event register capture
event bit, DTERn[CAP]. If DTERn[CAP] and DTXMRn[DMAEN] are set, a DMA request is asserted. If
DTERn[CAP] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted.
21.3.3
Each DMA timer can be configured to count up to a reference value. If the reference value is met,
DTERn[REF] is set.
21-8
Field
31–0
CNT
•
•
IPSBAR
If DTMRn[ORRI] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted.
If DTMRn[ORRI] and DTXMRn[DMAEN] are set, a DMA request is asserted.
Offset:
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Timer counter. Can be read at anytime without affecting counting and any write to this field clears it.
Functional Description
W
R
DMA Timer Counters (DTCNn)
Prescaler
Capture Mode
Reference Compare
0x00_040C (DTCN0)
0x00_044C (DTCN1)
0x00_048C (DTCN2)
0x00_04CC (DTCN3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 21-7. DMA Timer Counters (DTCNn)
Table 21-7. DTCNn Field Descriptions
CNT (32-bit timer counter value count)
Description
sys
divided by 1 or 16) or from the
8
7
Access: User read/write
6
Freescale Semiconductor
5
4
3
2
1
0