MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 52

IC MPU 32BIT 66MHZ 256-MAPBGA

MCF5282CVF80

Manufacturer Part Number
MCF5282CVF80
Description
IC MPU 32BIT 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet

Specifications of MCF5282CVF80

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Controller Family/series
ColdFire
Ram Memory Size
64KB
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of Pwm Channels
8
Digital Ic Case Style
MAPBGA
Rohs Compliant
No
Package
256MA-BGA
Device Core
ColdFire
Family Name
MCF528x
Maximum Speed
80 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
150
Interface Type
CAN/Ethernet/I2C/QSPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
12
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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ColdFire Core
2.2.4
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.
2-6
Field
7–5
X
N
Z
V
C
4
3
2
1
0
Reset:
BDM: LSB of Status Register (SR)
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
R
BDM: Load: 0x08F (A7)
Reserved, must be cleared.
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
result.
Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.
Zero condition code bit. Set if result equals zero; otherwise cleared.
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand
size; otherwise cleared.
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a
subtraction; otherwise cleared.
W
R
Condition Code Register (CCR)
Store: 0x18F (A7)
0x800 (OTHER_A7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
7
0
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 2-4. Stack Pointer Registers (A7 and OTHER_A7)
0
0
6
Figure 2-5. Condition Code Register (CCR)
Table 2-2. CCR Field Descriptions
0
0
5
X
4
Description
Address
N
3
OTHER_A7: Supervisor or BDM read/write
Access: A7: User or BDM read/write
Z
2
8
7
6
Freescale Semiconductor
Access: User read/write
5
V
1
4
3
BDM read/write
2
1
C
0
0

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