MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 657

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
Breakpoint registers must be carefully configured in a development system if the processor is executing.
The debug module contains no hardware interlocks, so TDR should be disabled while breakpoint registers
are loaded, after which TDR can be written to define the exact trigger. This prevents spurious breakpoint
triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU
is writing the debug’s registers (DSCLK must be inactive).
Note that the debug module requires the use of the internal bus to perform BDM commands. In Revision
A, if the processor is executing a tight loop that is contained within a single aligned longword, the
processor may never grant the internal bus to the debug module, for example:
label1: nop
or
label2: bra.w label2
The processor grants the internal bus if these loops are forced across two longwords.
30.7
This section specifies the ColdFire processor and debug module’s generation of the processor status (PST)
and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an
instruction is defined as follows:
where the {...} definition is optional operand information defined by the setting of the CSR.
The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST
value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the DDATA output {1,
2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions, CSR[BTB] provides the
capability to display the target instruction address on the DDATA output {2, 3, or 4 bytes} using a PST
value of {0x9, 0xA, or 0xB}.
30.7.1
Table 30-22
register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the destination
operand. For a given instruction, the optional operand data is displayed only for those effective addresses
referencing memory. The ‘DD’ nomenclature refers to the DDATA outputs.
Freescale Semiconductor
Instruction
addi.l
add.l
add.l
align4
bra.b label1
align4
Processor Status, DDATA Definition
User Instruction Set
shows the PST/DDATA specification for user-mode instructions. Rn represents any {Dn, An}
Operand Syntax
Table 30-22. PST/DDATA Specification for User-Mode Instructions
<ea>y,Rx
Dy,<ea>x
#imm,Dx
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
PST = 0x1, {PST = [0x89B], DDATA= operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST/DDATA
Debug Support
30-39