MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 725

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Freescale Semiconductor
IPSBAR + 0x111C
IPSBAR + 0x114C
IPSBAR + 0x1118
IPSBAR + 0x1120
IPSBAR + 0x1124
IPSBAR + 0x1144
IPSBAR + 0x1150
IPSBAR + 0x1180
IPSBAR + 0x1184
IPSBAR + 0x1188
0x1200-0x13FF
0x10_000A
0x10_000B
0x10_0000
0x10_0001
0x10_0002
0x10_0003
0x10_0004
0x10_0005
0x10_0006
0x10_0007
0x10_0008
0x10_0009
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
IPSBAR +
Address
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table A-3. Register Memory Map (continued)
RAM used to store management counters
(Reserved for MCF5214 and MCF5216)
Upper 32 bits of individual hash table
Lower 32 bits of individual hash table
Pointer to Transmit Descriptor Ring
Pointer to Receive Descriptor Ring
Upper 32-bits of group hash table
Lower 32-bits of group hash table
FIFO Receive Bound Register
Maximum Receive Buffer Size
Port DD Output Data Register
Port EH Output Data Register
Port EL Output Data Register
FIFO Receive Start Address
Port C Output Data Register
Port D Output Data Register
Port G Output Data Register
Port H Output Data Register
Port A Output Data Register
Port B Output Data Register
Port E Output Data Register
Port F Output Data Register
Port J Output Data Register
Transmit FIFO Watermark
GPIO Registers
Name
Mnemonic
MIB_RAM
PORTDD
PORTEH
PORTEL
EMRBR
PORTG
ERDSR
ETDSR
PORTB
PORTC
PORTD
PORTE
PORTH
PORTA
PORTF
PORTJ
TFWR
GAUR
FRBR
GALR
FRSR
IAUR
IALR
Register Memory Map
Size
32
32
32
32
32
32
32
32
32
32
32
8
8
8
8
8
8
8
8
8
8
8
8
A-13