MCF5282CVF80 Freescale Semiconductor, MCF5282CVF80 Datasheet - Page 306

• Manufacturer Part Number: MCF5282CVF80
• Description: IC MPU 32BIT 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF528x
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 150
• Interface Type: CAN/Ethernet/I2C/QSPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 12
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DMA Controller Module
16.4.5
In response to an event, the DMA controller writes to the appropriate DSRn bit,
to DSRn[DONE] results in action.
Table 16-4
16-10
14–0
Bits
Bits
15
7
6
5
4
3
2
DMA Status Registers (DSR0–DSR3)
describes DSRn fields.
Name
Name
REQ
BES
BED
CE
AT
—
—
—
Reserved, should be cleared.
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size,
or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing
a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved, should be cleared.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
AT is available only if MPARK[BCR24BIT] = 1.
DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer
or only the final transfer.
0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the
1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information
Reserved, should be cleared.
Bus error on destination
Address
result of an external request.
is displayed for both the read and write cycles.
Reset
Field
R/W
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 16-3. DCRn Field Descriptions (continued)
—
7
Figure 16-9. DMA Status Registers (DSRn)
Table 16-4. DSRn Field Descriptions
CE
6
IPSBAR + 0x110, 0x150, 0x190, 0x1D0
BES
5
BED
0000_0000
4
Description
Description
R/W
—
3
REQ
2
BSY
1
Figure
DONE
0
Freescale Semiconductor
16-9. Only a write