KMSC7119VM1200 Freescale Semiconductor, KMSC7119VM1200 Datasheet - Page 23

• Manufacturer Part Number: KMSC7119VM1200
• Description: DSP 16BIT W/DDR CTRLR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC711x StarCorer
• Type: Fixed Pointr

Specifications of KMSC7119VM1200

• Interface: Host Interface, I²C, UART
• Clock Rate: 300MHz
• Non-volatile Memory: ROM (8 kB)
• On-chip Ram: 464kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: 400-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.5.2.3
The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10.
2.5.2.4
The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown
in Table 11.
This bit along with the CKSEL determines the frequency range of the core clock.
2.5.2.5
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this
restriction.
Freescale Semiconductor
Note:
Note:
Note:
DDR 200 (PC-1600)
DDR 266 (PC-2100)
DDR 333 (PC-2600)
CLKCTRL[CKSEL]
CLKCTRL[RNG] Value
DDR Type
266 ≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz
This table results from the allowed range for F
frequency of the Divided Input Clock.
This table results from the allowed range for F
This table results from the allowed range for F
11
11
01
01
Multiplier Block (Loop) Output Range
Multiplication Factor Range
Allowed Core Clock Frequency Range
Core Clock Frequency Range When Using DDR Memory
1
0
Allowed Frequency
Range for DDR CK
CLKCTRL[RNG]
83–100 MHz
83–133 MHz
83–150 MHz
Table 12. Resulting Ranges Permitted for the Core Clock
1
0
1
0
Table 13. Core Clock Ranges When Using DDR
Table 11. F
Resulting
Division
Table 10. PLLMLTF Ranges
Factor
MSC7119 Data Sheet, Rev. 8
166 ≤ core clock ≤ 200 MHz
166 ≤ core clock ≤ 266 MHz
166 ≤ core clock ≤ 300 MHz
1
2
2
4
Loop
vco
OUT
Corresponding Range
for the Core Clock
, which is F
, which depends on clock selected via CLKCTRL[CKSEL].
. The minimum and maximum multiplication factors are dependent on the
vco
Frequency Ranges
Loop
66.5 ≤ core clock ≤ 133 MHz
266 ≤ core clock ≤ 300 MHz
133 ≤ core clock ≤ 266 MHz
133 ≤ core clock ≤ 266 MHz
266/Divided Input Clock
Minimum PLLMLTF Value
modified by CLKCTRL[RNG].
Allowed Range of F
Allowed Range
of Core Clock
266 ≤ F
133 ≤ F
vco
vco
≤ 532 MHz
≤ 266 MHz
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
vco
Limited by maximum core
frequency
Limited by range of PLL
Limited by range of PLL
Limited by range of PLL
532/Divided Input Clock
Maximum PLLMLTF Value
Comments
Electrical Characteristics
Comments
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