ADSP-BF538BBCZ-4F4 Analog Devices Inc, ADSP-BF538BBCZ-4F4 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF538BBCZ-4F4
• Description: IC, FLOAT-PT DSP, 16BIT, 400MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-4F4

• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Ram Size: 32KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 0.8/2.25/2.7V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 316
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / Rohs Status: Compliant

The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF538/ADSP-BF538F processors provide four oper-
ating modes, each with a different performance/power profile.
In addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the processor peripherals also reduces power consumption.
See
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 5. Power Settings
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally, an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of a wake-up
event enabled in the SIC_IWRx register causes the processor to
sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor will tran-
sition to the active mode. When in the sleep mode, system DMA
access to L1 memory is not supported.
Mode
Full On
Active
Sleep
Deep
Sleep
Hibernate Disabled —
Table 5
for a summary of the power settings for each mode.
PLL
Enabled
Enabled/
Disabled
Enabled
Disabled —
PLL
Bypassed
No
Yes
—
Core
Clock
(CCLK)
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
System
Clock
(SCLK)
Rev. D | Page 13 of 56 | July 2010
Internal
Power
(V
DDINT
)
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running, but will not be able to
access internal resources or external memory. This powered
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full-on mode after processor reset.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Also, disabling these clocks, sets the internal power
supply voltage (V
ings. To preserve the processor state, prior to removing power,
any critical information stored internally (memory contents,
register contents, and others) must be written to a nonvolatile
storage device.
Because V
external pins three-state, unless otherwise specified. This state
allows other devices that are connected to the processor to still
have power applied without drawing unwanted current.
There are a number of methods for wake up. The CAN module
can wake up the internal supply regulator. Additionally, the
GPW pin can be pulled low by any other device to wake up the
processor. Finally, the regulator can also be woken up by a real-
time clock wake-up event or by asserting the RESET pin. All
hibernate wake-up events initiate the hardware reset sequence.
Individual sources are enabled by the VR_CTL register.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables can be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register provides a
means of waking from hibernate state without disrupting a self-
refreshing SDRAM, provided there is also an external pull-
down on the SCKE pin.
Power Savings
As shown in
sors support three different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions. The 3.3 V
V
the RTC can remain functional when the rest of the chip is pow-
ered off. The 1.25 V VDDINT power domain supplies all the
DDRTC
power domain supplies the RTC I/O and logic so that
DDEXT
Table
is still supplied in clocks-disabled state, all of the
DDINT
ADSP-BF538/ADSP-BF538F
6, the ADSP-BF538/ADSP-BF538F proces-
) to 0 V to provide the greatest power sav-