ADSP-BF538BBCZ-4F4 Analog Devices Inc, ADSP-BF538BBCZ-4F4 Datasheet - Page 42

• Manufacturer Part Number: ADSP-BF538BBCZ-4F4
• Description: IC, FLOAT-PT DSP, 16BIT, 400MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-4F4

• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Ram Size: 32KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 0.8/2.25/2.7V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 316
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / Rohs Status: Compliant

ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Ports—Master Timing
Table 35
Table 35. Serial Peripheral Interface (SPI) Ports—Master Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
CPHA = 1
CPHA = 0
(OUTPUT)
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
SPIxMOSI
(OUTPUT)
SPIxMISO
SPIxSCK
and
(INPUT)
(INPUT)
Figure 27
Data Input Valid to SCKx Edge (Data Input Setup)
SCKx Sampling Edge to Data Input Invalid
SPIxSELy Low to First SCKx edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCKx Edge to SPIxSELy High
Sequential Transfer Delay
SCKx Edge to Data Out Valid (Data Out Delay)
SCKx Edge to Data Out Invalid (Data Out Hold)
t
SSPIDM
describe SPI ports master operations.
t
SDSCIM
t
HSPIDM
t
SPICLM
Figure 27. Serial Peripheral Interface (SPI) Ports—Master Timing
t
SPICHM
t
HDSPIDM
t
HDSPIDM
Rev. D | Page 42 of 56 | July 2010
t
DDSPIDM
t
SPICLK
t
DDSPIDM
t
SSPIDM
t
HDSM
t
HSPIDM
Min
9.0
–1.5
2 × t
2 × t
2 × t
4 × t
2 × t
2 × t
–1.0
t
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SPITDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
Max
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns