ADSP-BF538BBCZ-4F4 Analog Devices Inc, ADSP-BF538BBCZ-4F4 Datasheet - Page 24

• Manufacturer Part Number: ADSP-BF538BBCZ-4F4
• Description: IC, FLOAT-PT DSP, 16BIT, 400MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-4F4

• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Ram Size: 32KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 0.8/2.25/2.7V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 316
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / Rohs Status: Compliant

ADSP-BF538/ADSP-BF538F
The following tables describe the voltage/frequency require-
ments for the ADSP-BF538/ADSP-BF538F processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock
system clock
phase-locked loop operating conditions.
Table 11. Core Clock (CCLK) Requirements - 400 MHz Models
Table 12. Core Clock (CCLK) Requirements - 533 MHz Models
Table 13. Phase-Locked Loop Operating Conditions
Table 14. System Clock (SCLK) Requirements
1
2
Parameter
f
Parameter
f
f
f
f
f
Parameter
f
f
f
f
f
f
Parameter
f
f
t
Guaranteed to t
VCO
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SCLK
SCLK
SCLK
(= 1/f
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
SCLK
Voltage Controlled Oscillator (VCO) Frequency
1
) must be greater than or equal to t
(Table
SCLK
= 7.5 ns. See
14) specifications.
DDINT
DDINT
DDINT
DDINT
DDINT
Table 27 on page
= 1.14 V Minimum)
= 1.045 V Minimum)
= 0.95 V Minimum)
= 0.85 V Minimum)
= 0.8 V Minimum)
(Table 11
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
= 0.8 V Minimum)
= 1.2 V Minimum)
= 1.14 V Minimum)
= 1.045 V Minimum)
= 0.95 V Minimum)
= 0.85 V Minimum)
Table 13
CCLK
33.
≥ 1.14 V)
< 1.14 V)
and
.
Table
describes
Rev. D | Page 24 of 56 | July 2010
12) and
Internal Regulator
Setting
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Internal Regulator Setting Max
1.25 V
1.20 V
1.10 V
1.00 V
0.95 V
0.85 V
Min
50
Max
Max f
Max
133
100
Max
400
364
333
280
250
533
500
444
400
333
250
2
CCLK
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
Unit
MHz