ADSP-BF538BBCZ-4F4 Analog Devices Inc, ADSP-BF538BBCZ-4F4 Datasheet - Page 8

• Manufacturer Part Number: ADSP-BF538BBCZ-4F4
• Description: IC, FLOAT-PT DSP, 16BIT, 400MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-4F4

• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Ram Size: 32KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 0.8/2.25/2.7V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 316
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / Rohs Status: Compliant

ADSP-BF538/ADSP-BF538F
Table 3. System and Core Event Mapping (Continued)
Event Control
The ADSP-BF538/ADSP-BF538F processors provide the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 32 bits wide:
Event Source
DMA10 Interrupt (SPORT3 Rx)
DMA11 Interrupt (SPORT3 Tx)
DMA5 Interrupt (SPI0)
DMA14 Interrupt (SPI1)
DMA15 Interrupt (SPI2)
DMA6 Interrupt (UART0 Rx)
DMA7 Interrupt (UART0 Tx)
DMA16 Interrupt (UART1 Rx)
DMA17 Interrupt (UART1 Tx)
DMA18 Interrupt (UART2 Rx)
DMA19 Interrupt (UART2 Tx)
Timer0, Timer1, Timer2 Interrupts
TWI0 Interrupt
TWI1 Interrupt
CAN Receive Interrupt
CAN Transmit Interrupt
Port F GPIO Interrupts A and B
MDMA0 Stream 0 Interrupt
MDMA0 Stream 1 Interrupt
MDMA1 Stream 0 Interrupt
MDMA1 Stream 1 Interrupt
Software Watchdog Timer
• CEC interrupt latch register (ILAT) – The ILAT register
• CEC interrupt mask register (IMASK) – The IMASK regis-
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre-
sponding IMASK bit is cleared.
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
Core
Event Name
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG13
IVG13
IVG13
IVG13
IVG13
Rev. D | Page 8 of 56 | July 2010
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND
register contents are monitored by the SICs as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF538/ADSP-BF538F processors have two, inde-
pendent DMA controllers that support automated data transfers
with minimal overhead for the processor core. DMA transfers
can occur between the processor internal memories and any of
its DMA capable peripherals. Additionally, DMA transfers can
be accomplished between any of the DMA capable peripherals
and external devices connected to the external memory inter-
• CEC interrupt pending register (IPEND) – The IPEND
• SIC interrupt mask registers (SIC_IMASKx) – These regis-
• SIC interrupt status registers (SIC_ISRx) – As multiple
• SIC interrupt wake-up enable registers (SIC_IWRx) – By
may be read or written while in supervisor mode. General-
purpose interrupts can be globally enabled and disabled
with the STI and CLI instructions, respectively.
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
ters control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servic-
ing the event.
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled or in sleep mode when the event is generated.
(For more information, see Dynamic Power Management
on Page
13.)
Table 3 on Page
7.