ADSP-BF538BBCZ-4F4 Analog Devices Inc, ADSP-BF538BBCZ-4F4 Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF538BBCZ-4F4
• Description: IC, FLOAT-PT DSP, 16BIT, 400MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-4F4

• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Ram Size: 32KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 0.8/2.25/2.7V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 316
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / Rohs Status: Compliant

ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processors is saved on the
supervisor stack.
The ADSP-BF538/ADSP-BF538F processors’ event controllers
consist of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). The core event controller
works with the system interrupt controller to prioritize and con-
trol all system events. Conceptually, interrupts from the
peripherals enter into the SIC and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the processor.
Table 2
in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controllers (SIC) provides the mapping
and routing of events from the many peripheral interrupt
sources to the prioritized general-purpose interrupt inputs of
the CEC. Although the ADSP-BF538/ADSP-BF538F processors
provide a default mapping, programs can alter the mappings
and priorities of interrupt events by writing the appropriate val-
ues into the interrupt assignment registers (SIC_IARx).
Table 3
pings into the CEC.
• Emulation – An emulation event causes the processor to
• Reset – This event resets the processor.
• Nonmaskable interrupt (NMI) – The NMI event can be
• Exceptions – Events that occur synchronously to program
• Interrupts – Events that occur asynchronously to program
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
flow (the exception is taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
describes the inputs to the CEC, identifies their names
describes the inputs into the SIC and the default map-
Rev. D | Page 7 of 56 | July 2010
Table 2. Core Event Controller (CEC)
Table 3. System and Core Event Mapping
Priority
(0 is Highest) Event Class
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Source
PLL Wake-Up Interrupt
DMA Controller 0 Error
DMA Controller 1 Error
PPI Error Interrupt
SPORT0 Error Interrupt
SPORT1 Error Interrupt
SPORT2 Error Interrupt
SPORT3 Error Interrupt
SPI0 Error Interrupt
SPI1 Error Interrupt
SPI2 Error Interrupt
UART0 Error Interrupt
UART1 Error Interrupt
UART2 Error Interrupt
CAN Error Interrupt
Real-Time Clock Interrupts
DMA0 Interrupt (PPI)
DMA1 Interrupt (SPORT0 Rx)
DMA2 Interrupt (SPORT0 Tx)
DMA3 Interrupt (SPORT1 Rx)
DMA4 Interrupt (SPORT1 Tx)
DMA8 Interrupt (SPORT2 Rx)
DMA9 Interrupt (SPORT2 Tx)
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
ADSP-BF538/ADSP-BF538F
NMI
EVT Entry
EMU
RST
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Core
Event Name
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9