ADSP-BF538BBCZ-4F4 Analog Devices Inc, ADSP-BF538BBCZ-4F4 Datasheet - Page 31

• Manufacturer Part Number: ADSP-BF538BBCZ-4F4
• Description: IC, FLOAT-PT DSP, 16BIT, 400MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-4F4

• No. Of Bits: 16 Bit
• Frequency: 400MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Ram Size: 32KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 0.8/2.25/2.7V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 316
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / Rohs Status: Compliant

Asynchronous Memory Write Cycle Timing
Table 25
on Page 32
tions for synchronous and for asynchronous ARDY.
Table 25. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SARDY
HARDY
DDAT
ENDAT
DO
HO
and
describe asynchronous memory write cycle opera-
Table 26 on Page 32
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
DATA 15–0
ADDR19–1
CLKOUT
ABE1–0
AMSx
ARDY
AWE
and
Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
t
ENDAT
Figure 14
1
t
DO
1
2 CYCLES
and
SETUP
Rev. D | Page 31 of 56 | July 2010
Figure 15
t
SARDY
t
WRITE ACCESS
PROGRAMMED
DO
2 CYCLES
t
HARDY
t
SARDY
ACCESS
1 CYCLE
EXTEND
t
HARDY
1 CYCLE
t
HO
HOLD
t
HO
ADSP-BF538/ADSP-BF538F
t
DDAT
Min
4.0
0.0
1.0
0.8
Max
6.0
6.0
Unit
ns
ns
ns
ns
ns
ns