IC FLEX 10K FPGA 30K 208-RQFP

EPF10K30RI208-4

Manufacturer Part NumberEPF10K30RI208-4
DescriptionIC FLEX 10K FPGA 30K 208-RQFP
ManufacturerAltera
SeriesFLEX-10K®
EPF10K30RI208-4 datasheet
 


Specifications of EPF10K30RI208-4

Number Of Logic Elements/cells1728Number Of Labs/clbs216
Total Ram Bits12288Number Of I /o147
Number Of Gates69000Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case208-RQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2233  
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January 2003, ver. 4.2
Features...
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM)
(1)
Maximum system gates
Logic elements (LEs)
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
Maximum user I/O pins
Altera Corporation
DS-F10K-4.2
Includes
FLEX 10KA
®
The industry’s first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip (SOPC)
integration
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
Logic array for general logic functions
High density
10,000 to 250,000 typical gates (see
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
TM
MultiVolt
I/O interface support
5.0-V tolerant input pins in FLEX
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG) PCI
Local Bus Specification, Revision 2.2
FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
EPF10K10
EPF10K20
EPF10K10A
10,000
20,000
31,000
63,000
576
1,152
72
144
3
6
6,144
12,288
150
189
FLEX 10K
Embedded Programmable
Logic Device Family
Data Sheet
Tables 1
and 2)
®
10KA devices
EPF10K30
EPF10K40
EPF10K50
EPF10K30A
EPF10K50V
30,000
40,000
69,000
93,000
1,728
2,304
216
288
6
8
12,288
16,384
246
189
50,000
116,000
2,880
360
10
20,480
310
1

EPF10K30RI208-4 Summary of contents

  • Page 1

    ... Maximum system gates Logic elements (LEs) Logic array blocks (LABs) Embedded array blocks (EABs) Total RAM bits Maximum user I/O pins Altera Corporation DS-F10K-4.2 Includes FLEX 10KA ® The industry’s first embedded programmable logic device (PLD) family, providing System-on-a-Programmable-Chip (SOPC) integration – ...

  • Page 2

    ... Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices 5.0-V Devices EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 EPF10K130V EPF10K250A 130,000 250,000 211,000 310,000 6,656 12,160 832 1,520 16 20 32,768 40,960 470 470 Table 3 TM options for reduced clock 3.3-V Devices EPF10K10A EPF10K30A EPF10K50V EPF10K100A EPF10K130V EPF10K250A Altera Corporation ...

  • Page 3

    ... FineLine BGA packages maximize board space efficiency Software design support and automatic place-and-route provided by Altera development systems for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF and netlist files, library of parameterized modules (LPM), ...

  • Page 4

    ... PQFP RQFP 102 134 102 134 102 147 147 102 147 147 Note (1) 484-Pin 600-Pin FineLine BGA BGA 150 (2) 246 369 406 470 470 Altera Corporation 240-Pin PQFP RQFP 189 189 189 189 189 189 189 189 403-Pin PGA 310 ...

  • Page 5

    ... This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set. General Altera’ ...

  • Page 6

    ... FLEX 10K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers the EPC1, EPC2, EPC16, and EPC1441 configuration devices, which configure FLEX 10K devices via a serial data stream. Configuration data can also be downloaded from system RAM or from Altera’ ...

  • Page 7

    ... PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. ...

  • Page 8

    ... FLEX 10K architecture. Each group of LEs is combined into an LAB; LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each row and column of the FastTrack Interconnect. Altera Corporation ...

  • Page 9

    ... IOE (IOE) IOE IOE Column Interconnect IOE IOE Row Interconnect Logic Array IOE IOE Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Embedded Array Block (EAB) IOE IOE IOE IOE IOE EAB EAB IOE IOE IOE IOE IOE Embedded Array FLEX 10K devices provide six dedicated inputs that drive the flipflops’ ...

  • Page 10

    ... EAB’s self-timed RAM need only meet the setup and hold time specifications of the global clock. When used as RAM, each EAB can be configured in any of the following sizes: 256 8, 512 4, 1,024 2, or 2,048 Figure 2. EAB Memory Configurations 256 8 512 1. See Figure 2. 4 1,024 2 Altera Corporation 2,048 1 ...

  • Page 11

    ... If necessary, all EABs in a device can be cascaded to form a single RAM block. EABs can be cascaded to form RAM blocks 2,048 words without impacting timing. Altera’s software automatically combines EABs to meet a designer’s RAM specifications. EABs provide flexible options for driving and controlling clock signals. ...

  • Page 12

    ... EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have 22 EAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices have 26. 12 Row Interconnect Data Data In Out D Q Address D Q RAM/ROM 256 512 1,024 2,048 Column Interconnect 1 Altera Corporation 24 ...

  • Page 13

    ... EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have 30 LAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices have 34 LABs. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Logic Array Block Each LAB consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect ...

  • Page 14

    ... Each LE drives both the local and the FastTrack Interconnect. See Figure 6. Carry-In Cascade-In Carry Cascade Table Chain Chain (LUT) Clock Carry-Out Cascade-Out Register Bypass Programmable Register PRN D Q ENA CLRN Altera Corporation To FastTrack Interconnect To LAB Local Interconnect ...

  • Page 15

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet The programmable flipflop in the LE can be configured for operation. The clock, clear, and preset control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the output of the LE. The LE has two outputs that drive the interconnect ...

  • Page 16

    ... The final carry-out signal is routed to an LE, where it can be used as a general-purpose signal. Figure 7. Carry Chain Operation (n-bit Full Adder) Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain an LUT bn Carry Chain LUT Carry Chain s1 Register LE1 s2 Register LE2 sn Register LEn Register Carry-Out LEn + 1 Altera Corporation ...

  • Page 17

    ... LUT d[7..4] LUT d[(4 n -1)..(4 n -4)] LUT Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Cascade Chain With the cascade chain, the FLEX 10K architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De Morgan’ ...

  • Page 18

    ... LE—are directed to different destinations to implement the desired logic function. Three inputs to the LE provide clock, clear, and preset control for the register. The Altera software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers ...

  • Page 19

    ... Clearable Counter Mode Carry-In data1 (ena) data2 (nclr) data3 (data) data4 (nload) Note: (1) Packed registers cannot be used with the cascade chain. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Cascade-In (1) 4-Input LUT Cascade-Out Cascade-In 3-Input LUT 3-Input ...

  • Page 20

    ... For example adder, this output is the sum of three signals and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. Altera Corporation ...

  • Page 21

    ... Conversely signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The Altera software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’ ...

  • Page 22

    ... In any of the clear and preset modes, the chip-wide reset overrides all other signals. Registers with asynchronous presets may be preset when the chip-wide reset is asserted. Inversion can be used to implement the asynchronous preset. of how to enter a section of a design for the desired functionality. Figure 10 shows examples Altera Corporation ...

  • Page 23

    ... Chip-Wide Reset Asynchronous Load with Preset NOT labctrl1 (Asynchronous Load) labctrl2 (Preset) data3 (Data) NOT Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Asynchronous Preset Chip-Wide Reset labctrl1 or labctrl2 VCC PRN D Q CLRN D Chip-Wide Reset Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2 ...

  • Page 24

    ... If DATA3 is tied to V LABCTRL1 asynchronously loads a one into the register. Alternatively, the Altera software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore register is preset by only one of the two LABCTRL signals, the DATA3 input is not needed and can be used for one of the LE operating modes ...

  • Page 25

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet FastTrack Interconnect In the FLEX 10K architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, which is a series of continuous horizontal and vertical routing channels that traverse the device ...

  • Page 26

    ... Row Channels Each LE can drive two row channels each intersection, four row channels can drive column channels. Each LE can switch interconnect access with the adjacent LAB. To LAB Local Interconnect Column Channels To Other Columns From Adjacent LAB To Adjacent LAB To Other Rows Altera Corporation ...

  • Page 27

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet For improved routing, the row interconnect is comprised of a combination of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the LABs in half of the row. The EAB can be driven by the half-length channels in the left half of the row and by the full-length channels ...

  • Page 28

    ... LAB row B, column 3. IOE IOE IOE LAB LAB A2 A3 LAB LAB B2 B3 IOE IOE IOE See Figure 15 for details. IOE IOE To LAB A5 To LAB A4 Cascade & Carry Chains To LAB B5 To LAB B4 IOE IOE Altera Corporation IOE IOE See Figure 14 for details. IOE IOE ...

  • Page 29

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet I/O Element An I/O element (IOE) contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time output register for data that requires fast clock- to-output performance ...

  • Page 30

    ... CLK[3..2] 30 VCC VCC OE[7..0] VCC CLK[1..0] VCC ENA[5..0] VCC CLRN[1..0] Chip-Wide VCC OE Register D Q ENA CLRN Chip-Wide Reset Chip-Wide Output Enable Output Register D Q ENA Open-Drain CLRN Output Slew-Rate Control Reset Input Register D Q ENA CLRN Chip-Wide Reset Altera Corporation ...

  • Page 31

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Each IOE selects the clock, clear, clock enable, and output enable controls from a network of I/O control signals called the peripheral control bus. The peripheral control bus uses high-speed drivers to minimize signal skew across devices ...

  • Page 32

    ... Row D Row E Row E Row F Row F Row H EPF10K130V EPF10K250A Row C Row E Row G Row N Row K Row M Row H Row F Row D Row J Row L Row I Altera Corporation EPF10K50 EPF10K50V Row A Row B Row D Row F Row H Row J Row A Row C Row E Row G Row I Row J Row E Row G Row I Row P Row M ...

  • Page 33

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Signals on the peripheral control bus can also drive the four global signals, referred to as GLOBAL0 through GLOBAL3 in internally generated signal can drive the global signal, providing the same low-skew, low-delay characteristics for an internally generated signal as for a signal driven by an input ...

  • Page 34

    ... Each IOE can be driven by column channels via a multiplexer. The set of column channels that each IOE can access is different for each IOE. See Row Channels per Pin (m) 144 144 216 216 216 312 312 312 456 Figure 15. Altera Corporation ...

  • Page 35

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 15. FLEX 10K Column-to-IOE Connections The values for m and n are provided in Table 11. Column n Interconnect n n Each IOE can drive up to two column channels. Table 11 lists the FLEX 10K column-to-IOE interconnect resources. ...

  • Page 36

    ... FineLine BGA package. The Altera software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software generates pin-outs describing how to lay out a board to take advantage of this migration (see Figure 16. SameFrame Pin-Out Example ...

  • Page 37

    ... ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device. In designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to GCLK1. With the Altera software, GCLK1 can feed both the ClockLock and ClockBoost circuitry in the FLEX 10K device. However, when both circuits are used, the other clock pin (GCLK0) cannot be used ...

  • Page 38

    ... MultiVolt I/O interface, and power sequencing for FLEX 10K devices. The PCI pull-up clamping diode, slew-rate control, and open-drain output options are controlled pin-by-pin via Altera logic options. The MultiVolt I/O interface is controlled by connecting V a different voltage than V ...

  • Page 39

    ... It can also provide an additional wired-OR plane. Additionally, the Altera software can convert tri-state buffers with grounded data inputs to open- drain pins automatically. ...

  • Page 40

    ... MultiVolt I/O Support Levels (V) Input 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 2.5, 3.3, or 5.0 2.5, 3.3, or 5.0 power supplies can be powered in any CCINT Output 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 2.5 pins. CCIO Table 13. Altera Corporation ...

  • Page 41

    ... These instructions are used when configuring a FLEX 10K device via JTAG ports with a BitBlaster, or ByteBlasterMV or MasterBlaster download cable, or using a Jam File (.jam) or Jam Byte-Code File (.jbc) via an embedded processor. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet The instruction register length of FLEX 10K devices is 10 bits. The USERCODE register length in FLEX 10K devices is 32 bits ...

  • Page 42

    ... Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Jam Programming & Test Language Specification IDCODE (32 Bits) Manufacturer’s Identity (11 Bits) 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 Altera Corporation 1 (1 Bit) ( ...

  • Page 43

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 18 shows the timing requirements for the JTAG signals. Figure 18. JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven Table 16 shows the timing parameters and values for FLEX 10K devices. Table 16. JTAG Timing Parameters & ...

  • Page 44

    ... Multiple test patterns can be used 464 (703 ) [521 ] Device Output 250 (8. [481 Device input rise and fall times < Note (1) Min (2) –2.0 –2.0 –25 –65 –65 Altera Corporation VCC To Test System C1 (includes JIG capacitance) Max Unit 7 150 ° C 135 ° C 150 ° C 135 ° ...

  • Page 45

    ... O T Ambient temperature A T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Conditions (3), (4) (3), (4) (3), (4) For commercial use For industrial use For commercial use For industrial use ...

  • Page 46

    ... 1.0 MHz OUT Conditions 1.0 MHz 1.0 MHz 1.0 MHz OUT Notes (5), (6) Min Typ 2.0 V CCINT –0.5 2.4 2.4 V – 0.2 CCIO –10 –40 0.5 Note (10) Min Min Altera Corporation Max Unit + 0 0.45 V 0. Max Unit Note (10) Max ...

  • Page 47

    ... Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum V rise time is 100 ms. V ...

  • Page 48

    ... For commercial use For industrial use Note (1) Min (2) –0.5 –2.0 –25 –65 –65 Min 3.00 (3.00) 3.60 (3.60) 3.00 (3.00) 3.60 (3.60) -0 –40 0 –40 Altera Corporation Max Unit 4 150 ° C 135 ° C 150 ° C 135 ° C Max Unit V V 5.75 ...

  • Page 49

    ... C Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. ...

  • Page 50

    ... Under bias Ceramic packages, under bias PQFP, TQFP, RQFP, and BGA packages, under bias 3.3 V Room Temperature Output Voltage (V) O Note (1) Min (2) –0.5 –2.0 –25 –65 –65 Altera Corporation 3 Max Unit 4 150 ° C 135 ° C 150 ° C 135 ° C ...

  • Page 51

    ... O T Ambient temperature A T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Conditions (3), (4) (3), (4) (3), (4) (5) For commercial use For industrial use For commercial use For industrial use ...

  • Page 52

    ... V to –0.3 V (10 ground, no load ground, no load (11) I (6), (7) Min Typ Max 1 CCINT whichever is lower –0.5 0.3 V CCINT 2.4 V – 0.2 CCIO 0.9 V CCIO 2.1 2.0 1.7 0.45 0.2 0.1 V CCIO 0.2 0.4 0.7 –10 10 – Altera Corporation Unit ...

  • Page 53

    ... C Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC voltage input is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. ...

  • Page 54

    ... PCI bus with eight or fewer loads 3.3 V CCINT V = 3.3 V CCIO Room Temperature Output Voltage (V) Figure 23 shows the typical output drive characteristics of the EPF10K250A device with 3.3-V and 2.5 Moreover, device analysis CCIO Typical Output Current (mA Output Voltage ( CCIO 3.3 V CCINT V = 2.5 V CCIO Room Temperature Altera Corporation ...

  • Page 55

    ... Figure 23. Output Drive Characteristics for EPF10K250A Device 50 40 Typical Output Current (mA Timing Model Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet 3.3 V CCI NT Typical 3.3 V CCI O Output Room Temperature Current (mA Output Voltage (V) O The continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance and accurate simulation and timing analysis ...

  • Page 56

    ... Figure 24 shows the overall timing model, which maps the possible paths to and from the various elements of the FLEX 10K device. Interconnect Logic Element I/O Element Embedded Array Block Altera Corporation ...

  • Page 57

    ... Figure 25. FLEX 10K Device LE Timing Model Carry-In Data-In Control-In Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figures 25 through 27 show the delays that correspond to various paths and functions within the LE, IOE, and EAB timing models. Cascade-In LUT Delay ...

  • Page 58

    ... I/O pin timing. Output Delays Delays t IOCO t OD1 t IOCOMB t OD2 t IOSU t OD3 t IOH IOCLR t ZX1 t ZX2 t ZX3 t INREG Output Register EAB Output Delays t t EABCO EABOUT t EABBYPASS t EABSU t EABH t EABCH t EABCL Delay Data-Out Altera Corporation ...

  • Page 59

    ... LE register control signal delay register clock-to-output delay CO t Combinatorial delay COMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 28. Synchronous Bidirectional Pin External Timing Model Dedicated Clock Tables 32 through 36 describe the FLEX 10K device internal timing parameters ...

  • Page 60

    ... IOE input pad and buffer to IOE register delay INREG t IOE register feedback delay IOFD t IOE input pad and buffer to FastTrack Interconnect delay INCOMB 60 Note (1) Parameter Note (1) Parameter = V CCIO = low voltage CCIO = V CCIO = low voltage CCIO Conditions Conditions (2) CCINT ( ( (2) CCINT ( (4) Altera Corporation ...

  • Page 61

    ... Address hold time after falling edge of write pulse WAH t Write enable to data output valid delay WO t Data-in to data-out valid delay DD t Data-out delay EABOUT t Clock high time EABCH t Clock low time EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Note (1) Parameter Conditions (5) (5) (5) (5) 61 ...

  • Page 62

    ... EAB address setup time before rising edge of write pulse when not using EABWASU input registers t EAB address hold time after falling edge of write pulse when not using input EABWAH registers t EAB write enable to data output valid delay EABWO 62 Notes (1), (6) Parameter Conditions Altera Corporation ...

  • Page 63

    ... Clock-to-output delay for bidirectional pins with global clock at IOE register OUTCOBIDIR t Synchronous IOE output buffer disable delay XZBIDIR t Synchronous IOE output buffer enable delay, slow slew rate = off ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Note (1) Parameter Notes (8), (10) Parameter ...

  • Page 64

    ... These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. (8) External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative subset of signal paths is tested to approximate typical device applications. (9) Contact Altera Applications for test circuit specifications and test conditions. ...

  • Page 65

    ... EAB Synchronous Read WE Address a0 t EABDATASU CLK Data-Out EAB Synchronous Write (EAB Output Registers Used) WE din1 Data- Address t EABWESU CLK Data-Out Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet a1 t EABDATAH t EABDATACO din2 a2 t EABDATAH t EABDATASU t EABWCREG dout0 dout1 a2 t ...

  • Page 66

    ... Note (1) -4 Speed Grade Min Max 1.7 0.7 1.9 0.9 1.2 0.3 1.2 1.2 0.9 1.5 1.1 0.6 2.5 1.6 1.2 1.2 4.0 4.0 Altera Corporation Unit ...

  • Page 67

    ... IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 1.3 0.5 0.2 0.0 2.8 1.0 1.0 2.6 4.9 6.3 4.5 4.5 6.8 8.2 6.0 3.1 3 ...

  • Page 68

    ... Note (1) -4 Speed Grade Min Max 1.9 6.0 1.2 6.2 2.2 0.6 1.9 1.8 2.5 10.7 7.2 2.0 0.4 0.6 1.2 6.2 6.2 0.6 4.0 7.2 Altera Corporation Unit ...

  • Page 69

    ... EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 13.7 13.7 9.7 5.8 7.3 13.0 10.0 2.0 5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0 9 ...

  • Page 70

    ... Note (1) -4 Speed Grade Min Max 6.2 3.8 5.2 4.0 3.8 0.6 3.8 1.1 4.9 8.7 3.9 0.8 3.0 Note (1) -4 Speed Grade Min Max 6.6 3.8 5.2 4.0 3.8 0.6 3.9 1.6 5.5 9.4 5.6 0.8 3.0 Altera Corporation Unit Unit ...

  • Page 71

    ... ZXBIDIR Notes to tables: (1) All timing parameters are described in (2) Using register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 16.1 5.5 0.0 2.0 6 ...

  • Page 72

    ... Note (1) -4 Speed Grade Min Max 1.8 0.6 2.0 0.8 1.5 0.4 1.4 1.4 1.2 1.6 1.2 0.6 1.4 1.3 1.2 1.2 4.0 4.0 Altera Corporation Unit ...

  • Page 73

    ... IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 0.4 0.5 0.4 0.0 3.1 1.0 1.0 3.3 5.6 7.0 5.2 5.2 7.5 8.9 7.7 3.3 3 ...

  • Page 74

    ... Note (1) -4 Speed Grade Min Max 1.9 6.0 1.2 6.2 2.2 0.6 1.9 1.8 2.5 10.7 7.2 2.0 0.4 0.6 1.2 6.2 6.2 0.6 4.0 7.2 Altera Corporation Unit ...

  • Page 75

    ... EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 13.7 13.7 9.7 5.8 7.3 13.0 10.0 2.0 5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0 9 ...

  • Page 76

    ... Note (1) -4 Speed Grade Min Max 8.7 4.8 7.2 6.2 4.8 0.3 3.7 2.7 6.4 10.1 7.1 0.6 3.0 Note (1) -4 Speed Grade Min Max 9.4 4.8 7.2 6.2 4.8 0.3 3.7 3.2 6.4 10.6 7.1 0.6 3.0 Altera Corporation Unit Unit ...

  • Page 77

    ... OUTCO Table 56. EPF10K30, EPF10K40 & EPF10K50 Device External Bidirectional Timing Parameters Symbol t INSUBIDIR t INHBIDIR t OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 8.4 3.6 5.5 4.6 3.6 0.3 3.3 3.9 7.2 10 ...

  • Page 78

    ... Speed Grade Unit Min Max 2.0 ns 0.5 ns 2.0 ns 1.3 ns 1.2 ns 0.3 ns 1.4 ns 1.5 ns 1.3 ns 1.0 ns 1.4 ns 0.7 ns 2.6 ns 3.1 ns 1.4 ns 1.4 ns 4.0 ns 4.0 ns Altera Corporation ...

  • Page 79

    ... OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 0.0 0.4 0.4 0.0 4.5 5.0 0.4 0.5 0.6 3.6 5.6 6.9 5.5 5.5 7 ...

  • Page 80

    ... Note (1) -4 Speed Grade Max Min Max 1.5 1.9 4.8 6.0 1.0 1.2 5.0 6.2 1.0 2.2 0.5 0.6 1.5 1.9 1.8 2.5 8.7 10.7 7.2 2.0 0.4 0.6 1.2 5.0 6.2 5.0 6.2 0.5 0.6 4.0 7.2 Altera Corporation Unit ...

  • Page 81

    ... EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 12.1 12.1 13.7 8.6 9.7 5.2 5.8 6.5 7.3 11.6 13.0 8.8 1.7 4 ...

  • Page 82

    ... Note (1) -4 Speed Grade Max Min 19.1 8.0 0.0 11.1 2.0 Note (1) -4 Speed Grade Max Min 10.4 0.0 11.1 2.0 15.4 15.4 Altera Corporation Unit Max 8.8 ns 6.0 ns 10.8 ns 7.7 ns 6.0 ns 0.5 ns 5.5 ns 3.7 ns 9 ...

  • Page 83

    ... CGENR t CASC COMB PRE t CLR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 38 Tables 64 through 70 show EPF10K100 device internal and external timing parameters. -3 Speed Grade Max Min 1.5 0.4 1.6 0.9 0.9 0.2 1.1 1.2 1.1 ...

  • Page 84

    ... Speed Grade Max Min Max 0.0 0.0 0.5 0.7 0.4 0.9 0.0 0.0 6.7 0.7 0.7 1.6 4.0 5.0 6.3 7.3 7.7 8.7 6.2 6.8 6.2 6.8 8.5 9.1 9.9 10.5 9.0 10.5 – – 8.1 10.3 8.1 10.3 Altera Corporation Unit ...

  • Page 85

    ... WDSU t WDH t WASU t WAH EABOUT t EABCH t EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3DX Speed Grade -3 Speed Grade Min Max Min 1.5 4.8 1.0 5.0 1.0 0.5 1.5 1.5 1.5 2.0 2.0 8.7 5.8 5.8 1.6 1 ...

  • Page 86

    ... Note (1) -4 Speed Grade Max Min Max 13.7 17.0 17.0 11.9 7.2 9.0 16.0 10.0 12.5 2.0 3.4 5.6 0.0 5.8 0.0 5.8 0.0 2.7 0.0 9.5 11.8 Altera Corporation Unit ...

  • Page 87

    ... DCLK2LE circuitry t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t LABCARRY t LABCASC Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3DX Speed Grade -3 Speed Grade Min Max 10.3 4.8 7.3 6.2 2.3 4.8 2.3 0.4 4.9 5.1 10.0 14.9 6.9 ...

  • Page 88

    ... Note (1) -4 Speed Grade Max Min 10.4 0.0 11.1 2.0 15.3 15.3 – – – – – – in this data sheet. Unit Max 24 14 – ns Unit Max ns ns 14.3 ns 18 – ns – ns – ns Altera Corporation ...

  • Page 89

    ... CO t COMB PRE t CLR t 2 2.0 CL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 71 through 77 show EPF10K50V device internal and external timing parameters. -2 Speed Grade Max Min Max 0.9 1.0 0.1 0.5 0.5 0.8 0.4 0.4 ...

  • Page 90

    ... Min Max Min 1.9 0.5 0.4 0.0 3.4 3.9 1.0 1.4 0.7 3.9 – 7.6 3.8 3.8 – 7.5 7.0 2.3 2.3 Unit Max 2.1 ns 0.5 ns 0 0.7 ns 4.7 ns – ns 8.4 ns 4.6 ns 4.6 ns – ns 8.3 ns 9.0 ns 2.7 ns 2.7 ns Altera Corporation ...

  • Page 91

    ... WDH t 0.1 WASU t 0.1 WAH EABOUT t 2.0 EABCH t 6.0 EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.7 2.8 4.9 3.9 0.0 2.5 4.0 4.1 0.4 0.8 0.1 0.2 0.9 1.1 1 ...

  • Page 92

    ... Speed Grade Min Max Min 16.5 16.5 20.8 10.8 13.4 6.0 7.4 7.5 9.2 14.2 17.4 11.8 1.8 5.6 6.9 0.0 0.0 5.8 7.2 0.0 0.0 1.4 2.1 0.0 0.0 5.6 7.4 0.0 0.0 11.4 Unit Max 20 14 14.0 ns Altera Corporation ...

  • Page 93

    ... Table 77. EPF10K50V Device External Bidirectional Timing Parameters Symbol -1 Speed Grade Min t 2.0 INSUBIDIR t 0.0 INHBIDIR t 2.0 OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 4.7 6.0 2.5 2.6 4.4 5.9 2.5 3.9 2.5 2.6 0.2 ...

  • Page 94

    ... Note (1) -4 Speed Grade Max Min Max 1.8 0.7 1.7 0.6 0.8 0.3 0.4 1.0 1.2 2.4 0.9 0.7 0.3 0.0 3.1 3.1 4.0 4.0 Unit 2.3 ns 0.9 ns 2.2 ns 0.7 ns 1.0 ns 0.4 ns 0.5 ns 1.3 ns 1.5 ns 3.0 ns 1 3 Altera Corporation ...

  • Page 95

    ... OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 1.3 0.4 0.3 0.0 2.6 3.3 0.0 0.0 1.7 3.5 – 8.2 4.9 4.9 – ...

  • Page 96

    ... Note (1) -4 Speed Grade Max Min Max 2.4 2.4 4.7 4.7 2.4 2.4 4.7 4.7 0.9 0.9 0.6 0.6 0.8 0.8 1.8 0.0 7.1 7.1 4.7 5.9 0.0 5.0 0.0 7.1 7.1 7.1 7.1 3.1 3.1 4.0 4.7 Altera Corporation Unit ...

  • Page 97

    ... EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 11.2 11.1 14.2 8.5 10.8 3.7 4.7 7.6 9.7 14.0 17.8 11.1 3.6 4 ...

  • Page 98

    ... Note (1) -4 Speed Grade Max Min Max 19.1 24.2 11.0 0.0 9.9 2.0 11.3 Note (1) -4 Speed Grade Max Min Max 10.8 0.0 8.8 2.0 10.2 16.4 19.3 16.4 19.3 Altera Corporation Unit Unit Unit ...

  • Page 99

    ... Table 86. EPF10K10A Device IOE Timing Microparameters Symbol -1 Speed Grade Min t IOC t IOCO t IOCOMB t 0.8 IOSU Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 38 Tables 85 through 91 show EPF10K10A device internal and external timing parameters. -2 Speed Grade Max Min ...

  • Page 100

    ... Speed Grade Unit Min Max 1.3 ns 1.9 ns 1.9 ns 4.7 ns 10.5 ns 1.9 ns 1.9 ns 4.7 ns 10.5 ns 8.4 ns 5.0 ns 5.0 ns Altera Corporation ...

  • Page 101

    ... WDH t 0.6 WASU t 0.9 WAH EABOUT t 3.0 EABCH t 3.03 EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 3.3 3.9 1.0 1.3 2.6 3.1 2.7 3.2 0.0 0.0 1.2 1.4 0.1 0.2 1 ...

  • Page 102

    ... Note (1) -3 Speed Grade Unit Min Max 13.1 ns 13.1 ns 9.3 ns 3.2 ns 5.6 ns 14.8 ns 11.0 ns 2.0 ns 3.9 ns 0.0 ns 6.5 ns 0.0 ns 2.2 ns 0.0 ns 4.1 ns 0.0 ns 9.9 ns Altera Corporation ...

  • Page 103

    ... OUTCO Table 91. EPF10K10A Device External Bidirectional Timing Parameters Symbol t INSUBIDIR t INHBIDIR t OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 4.2 2.2 4.3 4.2 2.2 0.1 2.2 0.8 3.0 5.2 1.8 ...

  • Page 104

    ... Note (1) (Part Speed Grade Max Min Max 2.6 3.4 0.3 0.5 0.2 0.3 0.6 0.8 2.2 Unit Unit Altera Corporation ...

  • Page 105

    ... OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Note (1) -2 Speed Grade Max Min Max 1.1 0.7 0.8 1.9 2.2 4.8 5.6 7.0 8.2 2.2 2.6 2.2 2.6 5.1 6 ...

  • Page 106

    ... Note (1) -3 Speed Grade Min Max 8.5 1.8 3.7 3.2 0.2 2.6 0.3 1.9 0.3 6.5 5.9 0.2 0.2 0.2 0.2 6.4 6.4 0.6 4.0 5.9 Altera Corporation Unit ...

  • Page 107

    ... EABWESU t 0.0 EABWEH t 3.2 EABWDSU t 0.0 EABWDH t 3.7 EABWASU t 0.0 EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 9.7 11.6 11.6 7.1 4.5 4.7 11.6 9.2 11.0 1.7 2.1 2.7 0.0 3 ...

  • Page 108

    ... Note (1) -3 Speed Grade Max Min Max 13.0 17.0 3.9 0.0 6.2 2.0 8.3 Note (1) -3 Speed Grade Max Min 6.8 0.0 6.2 2.0 7.5 7.5 Altera Corporation Unit Unit Unit Max ns ns 8 ...

  • Page 109

    ... CO t COMB PRE t CLR t 2 2.5 CL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 38 Tables 99 through 105 show EPF10K100A device internal and external timing parameters. -2 Speed Grade Max Min 1.0 0.8 1.4 0.4 0.6 0.2 ...

  • Page 110

    ... Note (1) -3 Speed Grade Min Max 3.4 0.4 0.3 0.7 1.8 0.3 1.4 3.0 6.1 9.3 3.7 3.7 6.8 10.0 7.2 6.4 6.4 Altera Corporation Unit ...

  • Page 111

    ... WDH t 0.2 WASU t 0.0 WAH EABOUT t 2.5 EABCH t 3.2 EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.8 2.1 3.2 3.7 0.8 0.9 2.3 2.7 0.8 0.9 1.0 1.1 0.3 0.3 1 ...

  • Page 112

    ... Note (1) -3 Speed Grade Unit Min Max 9.2 ns 9.2 ns 7.4 ns 4.4 ns 4.7 ns 12.8 ns 8.2 ns 2.9 ns 5.1 ns 0.0 ns 3.8 ns 0.0 ns 4.6 ns 0.0 ns 2.6 ns 0.0 ns 6.9 ns Altera Corporation ...

  • Page 113

    ... OUTCO Table 105. EPF10K100A Device External Bidirectional Timing Parameters Symbol t INSUBIDIR t INHBIDIR t OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 4.8 2.0 2.4 2.6 2.0 0.1 1.5 5.5 7.0 8.5 3 ...

  • Page 114

    ... Note (1) -3 Speed Grade Max Min Max 1.0 1.4 1.3 1.6 2.3 2.7 0.4 0.5 1.6 1.9 0.3 0.3 0.6 0.6 1.0 1.1 0.8 1.0 1.3 1.6 0.7 0.9 0.6 0.7 1.7 1.6 0.8 0.9 0.8 0.9 3.5 3.5 Unit Altera Corporation ...

  • Page 115

    ... IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.2 1.3 0.4 0.4 0.8 0.9 0.7 0.7 3.1 0.3 1.2 1.3 3.2 3.6 5.9 6 ...

  • Page 116

    ... Note (1) -3 Speed Grade Min Max 1.7 1.7 1.3 6.7 0.8 0.0 0.2 5.0 0.9 5.9 7.5 1.7 0.2 0.2 0.2 5.5 5.5 0.2 3.5 7.5 Altera Corporation Unit ...

  • Page 117

    ... EABWESU t 0.0 EABWEH t 1.7 EABWDSU t 0.0 EABWDH t 0.9 EABWASU t 0.0 EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 6.1 6.8 6.8 5.1 6.4 6.6 17.8 5.7 6.4 0.7 0.8 5.1 0.0 9 ...

  • Page 118

    ... Note (1) -3 Speed Grade Max Min Max 17.0 20.0 9.4 0.0 8.9 2.0 10.4 Note (1) -3 Speed Grade Max Min 12.7 0.0 8.9 2.0 12.2 12.2 Altera Corporation Unit Unit Unit Max ns ns 10 ...

  • Page 119

    ... Input clock frequency (ClockBoost clock multiplication factor equals 2) CLK2 t Input clock period (ClockBoost clock multiplication factor equals 2) CLK2 Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 37 For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device ...

  • Page 120

    ... This value is calculated based on the amount of current that each LE typically consumes. The P IO load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). 1 Compared to the rest of the device, the embedded array consumes a negligible amount of power. Therefore, the embedded array can be ignored when calculating supply current ...

  • Page 121

    ... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet = Maximum operating frequency in MHz f MAX N = Total number of logic cells used in the device tog = Average percent of logic cells toggling at each clock LC (typically 12.5 Constant, shown in Table 114. FLEX 10K K Constant Values ...

  • Page 122

    ... Frequency (MHz) 122 EPF10K20 I Supply CC Current (mA EPF10K40 I Supply CC Current (mA EPF10K70 I Supply CC Current (mA 1,000 900 800 700 600 500 400 300 200 100 Frequency (MHz) 2,500 2,000 1,500 1,000 500 Frequency (MHz) 3,500 3,000 2,500 2,000 1,500 1,000 500 Frequency (MHz) Altera Corporation ...

  • Page 123

    ... EPF10K130V 2,000 1,500 I Supply CC Current (mA) 1,000 500 Frequency (MHz) EPF10K30A 400 300 I Supply CC Current (mA) 200 100 0 25 Frequency (MHz) Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet EPF10K50V I Supply CC Current (mA EPF10K10A I Supply CC Current (mA 100 EPF10K100A I Supply CC Current (mA 100 ...

  • Page 124

    ... I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode; normal device operation is called user mode 100 Frequency (MHz) Altera Corporation ...

  • Page 125

    ... FLEX 10KA or FLEX 10KE device. The programming or configuration files for EPF10K50 devices can program or configure an EPF10K50V device. However, Altera recommends recompiling a design for the EPF10K50V device when transferring it from the EPF10K50 device. Configuration Schemes ...

  • Page 126

    ... Parallel data source BitBlaster, MasterBlaster, or ByteBlasterMV download cable, or microprocessor with Jam STAPL file or Jam Byte-Code file See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. The information contained in the FLEX 10K Embedded Programmable Logic Device Family Data Sheet version 4.2 supersedes information published in previous versions ...

  • Page 127

    ... Notes: Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet 127 ...

  • Page 128

    ... San Jose, CA 95134 Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as (408) 544-7000 trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera http://www ...