IC FLEX 10K FPGA 30K 208-RQFP

EPF10K30RI208-4

Manufacturer Part NumberEPF10K30RI208-4
DescriptionIC FLEX 10K FPGA 30K 208-RQFP
ManufacturerAltera
SeriesFLEX-10K®
EPF10K30RI208-4 datasheet
 


Specifications of EPF10K30RI208-4

Number Of Logic Elements/cells1728Number Of Labs/clbs216
Total Ram Bits12288Number Of I /o147
Number Of Gates69000Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case208-RQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2233  
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Table 32. LE Timing Microparameters (Part 1 of 2)
Symbol
t
LUT delay for data-in
LUT
t
LUT delay for carry-in
CLUT
t
LUT delay for LE register feedback
RLUT
t
Data-in to packed register delay
PACKED
t
LE register enable delay
EN
t
Carry-in to carry-out delay
CICO
t
Data-in to carry-out delay
CGEN
t
LE register feedback to carry-out delay
CGENR
t
Cascade-in to cascade-out delay
CASC
t
LE register control signal delay
C
t
LE register clock-to-output delay
CO
t
Combinatorial delay
COMB
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Dedicated
Clock
Tables 32
through
36
describe the FLEX 10K device internal timing
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis.
Tables 37
timing parameters.
Note (1)
Parameter
OE Register
PRN
D
Q
t
XZBIDIR
t
ZXBIDIR
CLRN
t
OUTCOBIDIR
Output Register
PRN
D
Q
t
CLRN
t
Input Register
PRN
D
Q
CLRN
through
38
describe FLEX 10K external
Bidirectional
Pin
INSUBIDIR
INHBIDIR
Conditions
59