IC FLEX 10K FPGA 30K 208-RQFP

EPF10K30RI208-4

Manufacturer Part NumberEPF10K30RI208-4
DescriptionIC FLEX 10K FPGA 30K 208-RQFP
ManufacturerAltera
SeriesFLEX-10K®
EPF10K30RI208-4 datasheet
 


Specifications of EPF10K30RI208-4

Number Of Logic Elements/cells1728Number Of Labs/clbs216
Total Ram Bits12288Number Of I /o147
Number Of Gates69000Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case208-RQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2233  
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Notes to tables:
(1)
All timing parameters are described in
(2)
Using an LE to register the signal may provide a lower setup time.
(3)
This parameter is specified by characterization.
ClockLock &
ClockBoost
Timing
Parameters
Table 113. ClockLock & ClockBoost Parameters
Symbol
t
Input rise time
R
t
Input fall time
F
t
Input duty cycle
INDUTY
f
Input clock frequency (ClockBoost clock multiplication factor equals 1)
CLK1
t
Input clock period (ClockBoost clock multiplication factor equals 1)
CLK1
f
Input clock frequency (ClockBoost clock multiplication factor equals 2)
CLK2
t
Input clock period (ClockBoost clock multiplication factor equals 2)
CLK2
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Tables 32
through
37
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration.
Figure 31
specifications.
Figure 31. Specifications for the Incoming & Generated Clocks
The t
parameter refers to the nominal input clock period; the t
I
nominal output clock period.
t
CLK1
Input
Clock
t
t
R
F
t
OUTDUTY
ClockLock-
Generated
Clock
Table 113
summarizes the ClockLock and ClockBoost parameters.
(Part 1 of 2)
Parameter
in this data sheet.
illustrates the incoming and generated clock
parameter refers to the
O
t
t
INDUTY
I
t
t
t
I
I
INCLKSTB
t
t
t
t
t
O +
O –
O
JITTER
JITTER
Min
Typ
45
30
12.5
16
20
f
CLKDEV
Max
Unit
2
ns
2
ns
55
%
80
MHz
33.3
ns
50
MHz
62.5
ns
119