IC FLEX 10K FPGA 30K 208-RQFP

EPF10K30RI208-4

Manufacturer Part NumberEPF10K30RI208-4
DescriptionIC FLEX 10K FPGA 30K 208-RQFP
ManufacturerAltera
SeriesFLEX-10K®
EPF10K30RI208-4 datasheet
 


Specifications of EPF10K30RI208-4

Number Of Logic Elements/cells1728Number Of Labs/clbs216
Total Ram Bits12288Number Of I /o147
Number Of Gates69000Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case208-RQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2233  
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FLEX 10K Embedded Programmable Logic Device Family Data Sheet
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input look-up
table (LUT), a programmable flipflop, and dedicated signal paths for carry
and cascade functions. The eight LEs can be used to create medium-sized
blocks of logic—8-bit counters, address decoders, or state machines—or
combined across LABs to create larger logic blocks. Each LAB represents
about 96 usable gates of logic.
Signal interconnections within FLEX 10K devices and to and from device
pins are provided by the FastTrack Interconnect, a series of fast,
continuous row and column channels that run the entire length and width
of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer and a flipflop that can be used as either an output
or input register to feed input, output, or bidirectional signals. When used
with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 1.6 ns and
hold times of 0 ns; as outputs, these registers provide clock-to-output
times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
Figure 1
shows a block diagram of the FLEX 10K architecture. Each group
of LEs is combined into an LAB; LABs are arranged into rows and
columns. Each row also contains a single EAB. The LABs and EABs are
interconnected by the FastTrack Interconnect. IOEs are located at the end
of each row and column of the FastTrack Interconnect.
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Altera Corporation